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/kvm-unit-tests/lib/x86/asm/
H A Ddebugreg.h11 #define DR6_ACTIVE_LOW 0xffff0ff0
12 #define DR6_VOLATILE 0x0001e80f
15 #define DR6_TRAP0 BIT(0) /* DR0 matched */
21 #define DR6_BUS_LOCK BIT(11) /* Bus lock 0x800 */
22 #define DR6_BD BIT(13) /* General Detect 0x2000 */
23 #define DR6_BS BIT(14) /* Single-Step 0x4000 */
24 #define DR6_BT BIT(15) /* Task Switch 0x8000 */
25 #define DR6_RTM BIT(16) /* RTM / TSX 0x10000 */
27 #define DR7_FIXED_1 0x00000400 /* init/reset value, too */
28 #define DR7_VOLATILE 0xffff2bff
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/kvm-unit-tests/s390x/
H A Dadtl-status.c21 static int testflag = 0;
26 uint8_t vregs[0x200]; /* 0x000 */
27 uint8_t reserved200[0x400 - 0x200]; /* 0x200 */
28 struct gs_cb gs_cb; /* 0x400 */
29 uint8_t reserved420[0x800 - 0x420]; /* 0x420 */
30 uint8_t reserved800[0x1000 - 0x800]; /* 0x800 */
45 for (i = 0; i < n; i++) { in memisset()
88 memset(&adtl_status, 0xff, sizeof(adtl_status)); in test_store_adtl_status()
98 report(memisset(&adtl_status, 0xff, sizeof(adtl_status)), in test_store_adtl_status()
108 report(memisset(&adtl_status, 0xff, sizeof(adtl_status)), in test_store_adtl_status()
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/kvm-unit-tests/lib/x86/
H A Dapic-defs.h10 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
17 #define APIC_ID 0x20
19 #define APIC_LVR 0x30
20 #define APIC_LVR_MASK 0xFF00FF
21 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
22 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
24 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
28 #define APIC_XAPIC(x) ((x) >= 0x14)
29 #define APIC_TASKPRI 0x80
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/kvm-unit-tests/lib/
H A Dprintf.c40 if (npad > 0) { in print_str()
42 while (npad > 0) { in print_str()
51 if (npad < 0) { in print_str()
52 props.pad = ' '; /* ignore '0' flag with '-' flag */ in print_str()
54 while (npad < 0) { in print_str()
70 if ((c0 & 0xf800) != 0xd800) in utf16_to_utf32()
73 if (c0 & 0x0400) in utf16_to_utf32()
74 return 0xfffd; in utf16_to_utf32()
77 if ((c1 & 0xfc00) != 0xdc00) in utf16_to_utf32()
78 return 0xfffd; in utf16_to_utf32()
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H A Defi.c32 …e RISCV_EFI_BOOT_PROTOCOL_GUID EFI_GUID(0xccd15fec, 0x6f73, 0x4eec, 0x83, 0x95, 0x3e, 0x69, 0xe4,…
65 unsigned long key = 0, map_size = 0, desc_size = 0; in efi_get_memory_map()
70 if (status != EFI_BUFFER_TOO_SMALL || map_size == 0) in efi_get_memory_map()
112 for (i = 0; i < efi_system_table->nr_tables; i++) { in efi_get_system_config_table()
129 efi_rs_call(reset_system, EFI_RESET_SHUTDOWN, code, 0, NULL); in efi_exit()
136 unsigned long cmdline_addr = 0; in efi_convert_cmdline()
139 int options_bytes = 0, safe_options_bytes = 0; /* UTF-8 bytes */ in efi_convert_cmdline()
149 if (c < 0x80) { in efi_convert_cmdline()
150 if (c == L'\0' || c == L'\n') in efi_convert_cmdline()
166 options_bytes += 2 + (c >= 0x800); in efi_convert_cmdline()
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/kvm-unit-tests/powerpc/
H A Dcstart64.S15 #define P_HANDLER 0x2ff8
39 bl 0f
40 0: mflr r31
41 subi r31, r31, 0b - start /* QEMU's kernel load address */
49 li r0,0
50 std r0,0(r1)
69 std r4, P_HANDLER(0)
71 /* relocate vector table to base address 0x0 (MSR_IP = 0) */
78 li r6,0x100
88 stdx r0,0,r6
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/kvm-unit-tests/x86/
H A Dvmx.h21 } while (0)
27 } while (0)
38 } while (0)
53 char data[0];
191 VPID = 0x0000ul,
193 PINV = 0x0002ul,
195 EPTP_IDX = 0x0004ul,
198 GUEST_SEL_ES = 0x0800ul,
199 GUEST_SEL_CS = 0x0802ul,
200 GUEST_SEL_SS = 0x0804ul,
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H A Dvmx_tests.c53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" in ffs()
93 "mov %%rsp, %0\n\t" in vmenter_main()
99 : "g"(0xABCD)); in vmenter_main()
100 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); in vmenter_main()
109 if (regs.rax != 0xABCD) { in vmenter_exit_handler()
113 regs.rax = 0xFFFF; in vmenter_exit_handler()
137 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; in preemption_timer_init()
149 vmx_set_test_stage(0); in preemption_timer_main()
203 "preemption timer with 0 value"); in preemption_timer_exit_handler()
214 case 0: in preemption_timer_exit_handler()
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/kvm-unit-tests/lib/linux/
H A Dpci_regs.h30 #define PCI_VENDOR_ID 0x00 /* 16 bits */
31 #define PCI_DEVICE_ID 0x02 /* 16 bits */
32 #define PCI_COMMAND 0x04 /* 16 bits */
33 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
34 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
35 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
36 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
37 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
38 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
39 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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