Lines Matching +full:0 +full:x800
21 } while (0)
27 } while (0)
38 } while (0)
53 char data[0];
191 VPID = 0x0000ul,
193 PINV = 0x0002ul,
195 EPTP_IDX = 0x0004ul,
198 GUEST_SEL_ES = 0x0800ul,
199 GUEST_SEL_CS = 0x0802ul,
200 GUEST_SEL_SS = 0x0804ul,
201 GUEST_SEL_DS = 0x0806ul,
202 GUEST_SEL_FS = 0x0808ul,
203 GUEST_SEL_GS = 0x080aul,
204 GUEST_SEL_LDTR = 0x080cul,
205 GUEST_SEL_TR = 0x080eul,
206 GUEST_INT_STATUS = 0x0810ul,
207 GUEST_PML_INDEX = 0x0812ul,
210 HOST_SEL_ES = 0x0c00ul,
211 HOST_SEL_CS = 0x0c02ul,
212 HOST_SEL_SS = 0x0c04ul,
213 HOST_SEL_DS = 0x0c06ul,
214 HOST_SEL_FS = 0x0c08ul,
215 HOST_SEL_GS = 0x0c0aul,
216 HOST_SEL_TR = 0x0c0cul,
219 IO_BITMAP_A = 0x2000ul,
220 IO_BITMAP_B = 0x2002ul,
221 MSR_BITMAP = 0x2004ul,
222 EXIT_MSR_ST_ADDR = 0x2006ul,
223 EXIT_MSR_LD_ADDR = 0x2008ul,
224 ENTER_MSR_LD_ADDR = 0x200aul,
225 VMCS_EXEC_PTR = 0x200cul,
226 TSC_OFFSET = 0x2010ul,
227 TSC_OFFSET_HI = 0x2011ul,
228 APIC_VIRT_ADDR = 0x2012ul,
229 APIC_ACCS_ADDR = 0x2014ul,
230 POSTED_INTR_DESC_ADDR = 0x2016ul,
231 EPTP = 0x201aul,
232 EPTP_HI = 0x201bul,
233 VMREAD_BITMAP = 0x2026ul,
234 VMREAD_BITMAP_HI = 0x2027ul,
235 VMWRITE_BITMAP = 0x2028ul,
236 VMWRITE_BITMAP_HI = 0x2029ul,
237 EOI_EXIT_BITMAP0 = 0x201cul,
238 EOI_EXIT_BITMAP1 = 0x201eul,
239 EOI_EXIT_BITMAP2 = 0x2020ul,
240 EOI_EXIT_BITMAP3 = 0x2022ul,
241 PMLADDR = 0x200eul,
242 PMLADDR_HI = 0x200ful,
246 INFO_PHYS_ADDR = 0x2400ul,
249 VMCS_LINK_PTR = 0x2800ul,
250 VMCS_LINK_PTR_HI = 0x2801ul,
251 GUEST_DEBUGCTL = 0x2802ul,
252 GUEST_DEBUGCTL_HI = 0x2803ul,
253 GUEST_EFER = 0x2806ul,
254 GUEST_PAT = 0x2804ul,
255 GUEST_PERF_GLOBAL_CTRL = 0x2808ul,
256 GUEST_PDPTE = 0x280aul,
257 GUEST_BNDCFGS = 0x2812ul,
260 HOST_PAT = 0x2c00ul,
261 HOST_EFER = 0x2c02ul,
262 HOST_PERF_GLOBAL_CTRL = 0x2c04ul,
265 PIN_CONTROLS = 0x4000ul,
266 CPU_EXEC_CTRL0 = 0x4002ul,
267 EXC_BITMAP = 0x4004ul,
268 PF_ERROR_MASK = 0x4006ul,
269 PF_ERROR_MATCH = 0x4008ul,
270 CR3_TARGET_COUNT = 0x400aul,
271 EXI_CONTROLS = 0x400cul,
272 EXI_MSR_ST_CNT = 0x400eul,
273 EXI_MSR_LD_CNT = 0x4010ul,
274 ENT_CONTROLS = 0x4012ul,
275 ENT_MSR_LD_CNT = 0x4014ul,
276 ENT_INTR_INFO = 0x4016ul,
277 ENT_INTR_ERROR = 0x4018ul,
278 ENT_INST_LEN = 0x401aul,
279 TPR_THRESHOLD = 0x401cul,
280 CPU_EXEC_CTRL1 = 0x401eul,
283 VMX_INST_ERROR = 0x4400ul,
284 EXI_REASON = 0x4402ul,
285 EXI_INTR_INFO = 0x4404ul,
286 EXI_INTR_ERROR = 0x4406ul,
287 IDT_VECT_INFO = 0x4408ul,
288 IDT_VECT_ERROR = 0x440aul,
289 EXI_INST_LEN = 0x440cul,
290 EXI_INST_INFO = 0x440eul,
293 GUEST_LIMIT_ES = 0x4800ul,
294 GUEST_LIMIT_CS = 0x4802ul,
295 GUEST_LIMIT_SS = 0x4804ul,
296 GUEST_LIMIT_DS = 0x4806ul,
297 GUEST_LIMIT_FS = 0x4808ul,
298 GUEST_LIMIT_GS = 0x480aul,
299 GUEST_LIMIT_LDTR = 0x480cul,
300 GUEST_LIMIT_TR = 0x480eul,
301 GUEST_LIMIT_GDTR = 0x4810ul,
302 GUEST_LIMIT_IDTR = 0x4812ul,
303 GUEST_AR_ES = 0x4814ul,
304 GUEST_AR_CS = 0x4816ul,
305 GUEST_AR_SS = 0x4818ul,
306 GUEST_AR_DS = 0x481aul,
307 GUEST_AR_FS = 0x481cul,
308 GUEST_AR_GS = 0x481eul,
309 GUEST_AR_LDTR = 0x4820ul,
310 GUEST_AR_TR = 0x4822ul,
311 GUEST_INTR_STATE = 0x4824ul,
312 GUEST_ACTV_STATE = 0x4826ul,
313 GUEST_SMBASE = 0x4828ul,
314 GUEST_SYSENTER_CS = 0x482aul,
315 PREEMPT_TIMER_VALUE = 0x482eul,
318 HOST_SYSENTER_CS = 0x4c00ul,
321 CR0_MASK = 0x6000ul,
322 CR4_MASK = 0x6002ul,
323 CR0_READ_SHADOW = 0x6004ul,
324 CR4_READ_SHADOW = 0x6006ul,
325 CR3_TARGET_0 = 0x6008ul,
326 CR3_TARGET_1 = 0x600aul,
327 CR3_TARGET_2 = 0x600cul,
328 CR3_TARGET_3 = 0x600eul,
331 EXI_QUALIFICATION = 0x6400ul,
332 IO_RCX = 0x6402ul,
333 IO_RSI = 0x6404ul,
334 IO_RDI = 0x6406ul,
335 IO_RIP = 0x6408ul,
336 GUEST_LINEAR_ADDRESS = 0x640aul,
339 GUEST_CR0 = 0x6800ul,
340 GUEST_CR3 = 0x6802ul,
341 GUEST_CR4 = 0x6804ul,
342 GUEST_BASE_ES = 0x6806ul,
343 GUEST_BASE_CS = 0x6808ul,
344 GUEST_BASE_SS = 0x680aul,
345 GUEST_BASE_DS = 0x680cul,
346 GUEST_BASE_FS = 0x680eul,
347 GUEST_BASE_GS = 0x6810ul,
348 GUEST_BASE_LDTR = 0x6812ul,
349 GUEST_BASE_TR = 0x6814ul,
350 GUEST_BASE_GDTR = 0x6816ul,
351 GUEST_BASE_IDTR = 0x6818ul,
352 GUEST_DR7 = 0x681aul,
353 GUEST_RSP = 0x681cul,
354 GUEST_RIP = 0x681eul,
355 GUEST_RFLAGS = 0x6820ul,
356 GUEST_PENDING_DEBUG = 0x6822ul,
357 GUEST_SYSENTER_ESP = 0x6824ul,
358 GUEST_SYSENTER_EIP = 0x6826ul,
361 HOST_CR0 = 0x6c00ul,
362 HOST_CR3 = 0x6c02ul,
363 HOST_CR4 = 0x6c04ul,
364 HOST_BASE_FS = 0x6c06ul,
365 HOST_BASE_GS = 0x6c08ul,
366 HOST_BASE_TR = 0x6c0aul,
367 HOST_BASE_GDTR = 0x6c0cul,
368 HOST_BASE_IDTR = 0x6c0eul,
369 HOST_SYSENTER_ESP = 0x6c10ul,
370 HOST_SYSENTER_EIP = 0x6c12ul,
371 HOST_RSP = 0x6c14ul,
372 HOST_RIP = 0x6c16ul
380 VMX_EXC_NMI = 0,
464 PIN_EXTINT = 1ul << 0,
495 CPU_VIRT_APIC_ACCESSES = 1ul << 0,
513 VMX_INTR_TYPE_EXT_INTR = 0,
523 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
524 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
525 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
526 #define INTR_INFO_UNBLOCK_NMI_MASK 0x1000 /* 12 */
527 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
531 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
543 #define GUEST_INTR_STATE_STI (1 << 0)
581 ENTRY_FAIL_DEFAULT = 0,
589 "xchg %rcx, regs+0x8\n\t" \
590 "xchg %rdx, regs+0x10\n\t" \
591 "xchg %rbx, regs+0x18\n\t" \
592 "xchg %rbp, regs+0x28\n\t" \
593 "xchg %rsi, regs+0x30\n\t" \
594 "xchg %rdi, regs+0x38\n\t" \
595 "xchg %r8, regs+0x40\n\t" \
596 "xchg %r9, regs+0x48\n\t" \
597 "xchg %r10, regs+0x50\n\t" \
598 "xchg %r11, regs+0x58\n\t" \
599 "xchg %r12, regs+0x60\n\t" \
600 "xchg %r13, regs+0x68\n\t" \
601 "xchg %r14, regs+0x70\n\t" \
602 "xchg %r15, regs+0x78\n\t"
608 "xchg %%rcx, regs+0x8\n\t" \
609 "xchg %%rdx, regs+0x10\n\t" \
610 "xchg %%rbx, regs+0x18\n\t" \
611 "xchg %%rbp, regs+0x28\n\t" \
612 "xchg %%rsi, regs+0x30\n\t" \
613 "xchg %%rdi, regs+0x38\n\t" \
614 "xchg %%r8, regs+0x40\n\t" \
615 "xchg %%r9, regs+0x48\n\t" \
616 "xchg %%r10, regs+0x50\n\t" \
617 "xchg %%r11, regs+0x58\n\t" \
618 "xchg %%r12, regs+0x60\n\t" \
619 "xchg %%r13, regs+0x68\n\t" \
620 "xchg %%r14, regs+0x70\n\t" \
621 "xchg %%r15, regs+0x78\n\t"
625 #define VMX_IO_SIZE_MASK 0x7
626 #define _VMX_IO_BYTE 0
631 #define VMX_IO_OUT 0
635 #define VMX_IO_PORT_MASK 0xFFFF0000
638 #define VMX_TEST_START 0
646 #define HYPERCALL_MASK 0xFFF
647 #define HYPERCALL_VMEXIT 0x1
648 #define HYPERCALL_VMABORT 0x2
649 #define HYPERCALL_VMSKIP 0x3
652 #define EPTP_PG_WALK_LEN_MASK 0x38ul
653 #define EPTP_RESERV_BITS_MASK 0x1ful
654 #define EPTP_RESERV_BITS_SHIFT 0x7ul
657 #define EPT_MEM_TYPE_UC 0ul
671 #define EPT_MEM_TYPE_MASK 0x7ul
675 #define EPT_CAP_EXEC_ONLY (1ull << 0)
703 #define EPT_VLT_RD (1ull << 0)
720 #define MAGIC_VAL_1 0x12345678ul
721 #define MAGIC_VAL_2 0x87654321ul
722 #define MAGIC_VAL_3 0xfffffffful
723 #define MAGIC_VAL_4 0xdeadbeeful
728 #define INVVPID_ADDR 0
733 #define ACTV_ACTIVE 0
740 * Bit 0: High-access
746 #define VMCS_FIELD_HIGH_SHIFT (0)
824 return (ctrl_cpu_rev[0].clr & CPU_SECONDARY) && in is_vpid_supported()
848 /* -1 on VM-Fail, 0 on success, >1 on fault */
857 "setbe %0\n\t" in __vmxon_safe()
859 "1: movb $0, %0\n\t" in __vmxon_safe()
884 asm volatile("push %1; popf; vmxoff; setbe %0\n\t" in vmx_off()
894 asm volatile ("push %1; popf; vmptrld %2; setbe %0" in make_vmcs_current()
904 asm volatile ("push %1; popf; vmclear %2; setbe %0" in vmcs_clear()
912 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); in vmcs_read()
924 asm volatile ("vmread %1, %0" : "=m" (val) : "r" ((u64)enc) : "cc"); in vmcs_readm()
950 asm volatile ("vmwrite %1, %2; setbe %0" in vmcs_write()
971 asm volatile ("push %2; popf; vmptrst %1; setbe %0" in vmcs_save()
984 } operand = {eptp, 0}; in __invept()
985 asm volatile("push %1; popf; invept %2, %3; setbe %0" in __invept()
987 return failed ? -1: 0; in __invept()
1001 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" in __invvpid()
1003 return failed ? -1: 0; in __invvpid()
1039 #define ABORT_ON_EARLY_VMENTRY_FAIL 0x1
1040 #define ABORT_ON_INVALID_GUEST_STATE 0x2