Lines Matching +full:0 +full:x800

15 #define P_HANDLER	0x2ff8
39 	bl	0f
40 0:	mflr	r31
41 	subi	r31, r31, 0b - start	/* QEMU's kernel load address */
49 	li	r0,0
50 	std	r0,0(r1)
69 	std	r4, P_HANDLER(0)
71 	/* relocate vector table to base address 0x0 (MSR_IP = 0) */
78 	li	r6,0x100
88 	stdx	r0,0,r6
90 	dcbst	0,r6
93 	icbi	0,r6
94 	cmpld	0,r6,r5
108 	cmpwi	r3, 0
112 	stw	r4, 0(r3)
122 	lwz	r3, 0(r3)
140 	bl	0f
141 0:	mflr	r31
142 	subi	r31, r31, 0b - start	/* QEMU's kernel load address */
147 	li	r8,0
148 	li	r7,0
163 	li	r0,0
164 	std	r0,0(r1)
194 	ld	r10, 0(r11)
196 	cmpdi	r10,0
238 	std	r0,0(r1) /* Backchain from interrupt stack to regular stack */
252 	bl	0f
253 0:	mflr	r31
254 	subi	r31, r31, 0b - start_text
284 	.irp i, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 \
298 /* [H]VECTOR must not be more than 8 instructions to fit in 0x20 vectors */
308 	SAVE_GPR(0,r1)
325 	SAVE_GPR(0,r1)
333 	. = 0x100
337 VECTOR(0x100)
338 VECTOR(0x200)
339 VECTOR(0x300)
340 VECTOR(0x380)
341 VECTOR(0x400)
342 VECTOR(0x480)
343 VECTOR(0x500)
344 VECTOR(0x600)
345 VECTOR(0x700)
346 VECTOR(0x800)
347 VECTOR(0x900)
348 HVECTOR(0x980)
349 VECTOR(0xa00)
350 VECTOR(0xc00)
351 VECTOR(0xd00)
352 HVECTOR(0xe00)
353 HVECTOR(0xe20)
354 HVECTOR(0xe40)
355 HVECTOR(0xe60)
356 HVECTOR(0xe80)
357 HVECTOR(0xea0)
358 VECTOR(0xf00)
359 VECTOR(0xf20)
360 VECTOR(0xf40)
361 VECTOR(0xf60)
362 HVECTOR(0xf80)
368 	ld	r0, P_HANDLER(0)
384 	ld	r0, P_HANDLER(0)
400 	.llong	0