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/linux-3.3/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7757.c26 .mapbase = 0xfe4b0000, /* SCIF2 */
36 .id = 0,
43 .mapbase = 0xfe4c0000, /* SCIF3 */
60 .mapbase = 0xfe4d0000, /* SCIF4 */
77 .channel_offset = 0x04,
78 .timer_bit = 0,
83 [0] = {
84 .start = 0xfe430008,
85 .end = 0xfe430013,
96 .id = 0,
[all …]
/linux-3.3/arch/powerpc/include/asm/
Ddcr-regs.h28 #define DCRN_CPR0_CONFIG_ADDR 0xc
29 #define DCRN_CPR0_CONFIG_DATA 0xd
32 #define DCRN_SDR0_CONFIG_ADDR 0xe
33 #define DCRN_SDR0_CONFIG_DATA 0xf
35 #define SDR0_PFC0 0x4100
36 #define SDR0_PFC1 0x4101
37 #define SDR0_PFC1_EPS 0x1c00000
39 #define SDR0_PFC1_RMII 0x02000000
40 #define SDR0_MFR 0x4300
41 #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
[all …]
Dreg_a2.h15 #define SPRN_TENSR 0x1b5
16 #define SPRN_TENS 0x1b6 /* Thread ENable Set */
17 #define SPRN_TENC 0x1b7 /* Thread ENable Clear */
19 #define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */
20 #define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */
21 #define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */
22 #define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
23 #define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
24 #define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
25 #define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
[all …]
Dmmu-8xx.h15 #define MI_GPM 0x80000000 /* Set domain manager mode */
16 #define MI_PPM 0x40000000 /* Set subpage protection */
17 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
18 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
19 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
20 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
21 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
24 * Ks = 0, Kp = 1.
27 #define MI_Ks 0x80000000 /* Should not be set */
28 #define MI_Kp 0x40000000 /* Should always be set */
[all …]
/linux-3.3/drivers/net/wireless/b43/
Ddma.h18 #define B43_DMA32_TXCTL 0x00
19 #define B43_DMA32_TXENABLE 0x00000001
20 #define B43_DMA32_TXSUSPEND 0x00000002
21 #define B43_DMA32_TXLOOPBACK 0x00000004
22 #define B43_DMA32_TXFLUSH 0x00000010
23 #define B43_DMA32_TXPARITYDISABLE 0x00000800
24 #define B43_DMA32_TXADDREXT_MASK 0x00030000
26 #define B43_DMA32_TXRING 0x04
27 #define B43_DMA32_TXINDEX 0x08
28 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/linux-3.3/arch/arm/mach-mxs/
Dregs-clkctrl-mx23.h31 #define HW_CLKCTRL_PLLCTRL0 (0x00000000)
32 #define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
33 #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34 #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
37 #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
40 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
41 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
42 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
43 #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
45 #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
[all …]
Dregs-clkctrl-mx28.h29 #define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
30 #define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
31 #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32 #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
35 #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
38 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
39 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
40 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
41 #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
43 #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
[all …]
/linux-3.3/drivers/net/usb/
Dsmsc75xx.h25 #define TX_CMD_A_LSO (0x08000000)
26 #define TX_CMD_A_IPE (0x04000000)
27 #define TX_CMD_A_TPE (0x02000000)
28 #define TX_CMD_A_IVTG (0x01000000)
29 #define TX_CMD_A_RVTG (0x00800000)
30 #define TX_CMD_A_FCS (0x00400000)
31 #define TX_CMD_A_LEN (0x000FFFFF)
33 #define TX_CMD_B_MSS (0x3FFF0000)
36 #define TX_CMD_B_VTAG (0x0000FFFF)
39 #define RX_CMD_A_ICE (0x80000000)
[all …]
/linux-3.3/drivers/staging/slicoss/
Dslichw.h44 #define PCI_VENDOR_ID_ALACRITECH 0x139A
45 #define SLIC_1GB_DEVICE_ID 0x0005
46 #define SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */
48 #define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
54 #define SLIC_RCVBUF_TAILSIZE 0
59 #define VGBSTAT_XPERR 0x40000000
61 #define VGBSTAT_XCSERR 0x23
62 #define VGBSTAT_XUFLOW 0x22
63 #define VGBSTAT_XHLEN 0x20
64 #define VGBSTAT_NETERR 0x01000000
[all …]
/linux-3.3/arch/mips/include/asm/mach-ip32/
Ddma-coherence.h18 * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
19 * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
21 * 3. All other devices see memory as one big chunk at 0x40000000
27 #define RAM_OFFSET_MASK 0x3fffffffUL
78 return 0; in plat_dma_supported()
91 return 0; in plat_dma_mapping_error()
96 return 0; /* IP32 is non-cohernet */ in plat_device_is_coherent()
/linux-3.3/arch/x86/platform/olpc/
Dolpc-xo1-pm.c35 } ofw_bios_entry = { 0xF0000 + PAGE_OFFSET, __KERNEL_CS };
60 r = olpc_ec_cmd(EC_SET_SCI_INHIBIT, NULL, 0, NULL, 0); in xo1_power_state_enter()
69 saved_sci_mask &= 0xffff0000; in xo1_power_state_enter()
80 olpc_ec_cmd(EC_SET_SCI_INHIBIT_RELEASE, NULL, 0, NULL, 0); in xo1_power_state_enter()
86 olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0); in xo1_power_state_enter()
87 olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0); in xo1_power_state_enter()
89 return 0; in xo1_power_state_enter()
99 __asm__("movl %0,%%eax" : : "r" (pgd_addr)); in xo1_do_sleep()
102 __asm__("movb $0x34, %al\n\t" in xo1_do_sleep()
103 "outb %al, $0x70\n\t" in xo1_do_sleep()
[all …]
/linux-3.3/drivers/net/ethernet/intel/igb/
De1000_82575.h46 #define E1000_SW_SYNCH_MB 0x00000100
47 #define E1000_STAT_DEV_RST_SET 0x00100000
48 #define E1000_CTRL_DEV_RST 0x20000000
53 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
54 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
55 #define E1000_SRRCTL_DROP_EN 0x80000000
56 #define E1000_SRRCTL_TIMESTAMP 0x40000000
58 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
59 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
60 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
[all …]
/linux-3.3/arch/arm/mach-pxa/include/mach/
Ddebug-macro.S17 mov \rp, #0x00100000
18 orr \rv, \rp, #io_p2v(0x40000000) @ virtual
19 orr \rp, \rp, #0x40000000 @ physical
/linux-3.3/drivers/net/wireless/brcm80211/brcmsmac/phy/
Dphytbl_lcn.c21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
25 0x00000000,
26 0x00000000,
27 0x00000000,
28 0x00000000,
29 0x00000004,
30 0x00000000,
[all …]
/linux-3.3/drivers/net/wireless/rt2x00/
Drt2800pci.h40 #define TX_QUEUE_REG_OFFSET 0x10
50 #define FIRMWARE_IMAGE_BASE 0x2000
65 #define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
70 #define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
71 #define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
72 #define TXD_W1_BURST FIELD32(0x00008000)
73 #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
74 #define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
75 #define TXD_W1_DMA_DONE FIELD32(0x80000000)
80 #define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
[all …]
/linux-3.3/drivers/net/ethernet/sis/
Dsis900.h18 #define SIS900_TOTAL_SIZE 0x100
22 cr=0x0, //Command Register
23 cfg=0x4, //Configuration Register
24 mear=0x8, //EEPROM Access Register
25 ptscr=0xc, //PCI Test Control Register
26 isr=0x10, //Interrupt Status Register
27 imr=0x14, //Interrupt Mask Register
28 ier=0x18, //Interrupt Enable Register
29 epar=0x18, //Enhanced PHY Access Register
30 txdp=0x20, //Transmit Descriptor Pointer Register
[all …]
/linux-3.3/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb_82599.h32 #define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
35 #define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
38 #define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
39 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
40 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
41 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
44 #define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
53 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
54 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
56 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
[all …]
/linux-3.3/drivers/gpu/drm/nouveau/
Dnva3_copy.c48 ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC | in nva3_copy_context_new()
53 nv_wo32(ramin, 0xc0, 0x00190000); in nva3_copy_context_new()
54 nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1); in nva3_copy_context_new()
55 nv_wo32(ramin, 0xc8, ctx->vinst); in nva3_copy_context_new()
56 nv_wo32(ramin, 0xcc, 0x00000000); in nva3_copy_context_new()
57 nv_wo32(ramin, 0xd0, 0x00000000); in nva3_copy_context_new()
58 nv_wo32(ramin, 0xd4, 0x00000000); in nva3_copy_context_new()
63 return 0; in nva3_copy_context_new()
86 inst |= 0x40000000; in nva3_copy_context_del()
89 nv_wr32(dev, 0x104048, 0x00000000); in nva3_copy_context_del()
[all …]
Dnv20_graph.c10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
54 return 0; in nv20_graph_unload_context()
63 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); in nv20_graph_unload_context()
[all …]
Dnvc0_copy.c57 nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->linst)); in nvc0_copy_context_new()
62 return 0; in nvc0_copy_context_new()
69 return 0; in nvc0_copy_object_new()
81 inst |= 0x40000000; in nvc0_copy_context_del()
84 nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000); in nvc0_copy_context_del()
86 if (nv_rd32(dev, pcopy->fuc + 0x050) == inst) in nvc0_copy_context_del()
87 nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000); in nvc0_copy_context_del()
89 if (nv_rd32(dev, pcopy->fuc + 0x054) == inst) in nvc0_copy_context_del()
90 nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000); in nvc0_copy_context_del()
92 nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003); in nvc0_copy_context_del()
[all …]
/linux-3.3/drivers/isdn/hisax/
Dbkm_ax.h23 #define PLX_ADDR_PLX 0x14 /* Addr PLX configuration */
24 #define PLX_ADDR_ISAC 0x18 /* Addr ISAC */
25 #define PLX_ADDR_HSCX 0x1C /* Addr HSCX */
26 #define PLX_ADDR_ALE 0x20 /* Addr ALE */
27 #define PLX_ADDR_ALEPLUS 0x24 /* Next Addr behind ALE */
29 #define PLX_SUBVEN 0x2C /* Offset SubVendor */
30 #define PLX_SUBSYS 0x2E /* Offset SubSystem */
42 volatile u_int i20VDispTop; /* Offset 0C */
57 #define sysRESET 0x01000000 /* bit 24:Softreset (Low) */
58 /* GPIO 4...0: Output fixed for our cfg! */
[all …]
/linux-3.3/arch/m68k/configs/
Dm5208evb_defconfig25 CONFIG_RAMBASE=0x40000000
26 CONFIG_RAMSIZE=0x2000000
27 CONFIG_VECTORBASE=0x40000000
28 CONFIG_KERNELBASE=0x40020000
/linux-3.3/arch/m68k/fpsp040/
Dget_op.S9 | determines the opclass (0, 2, or 3) and branches to the
17 | - For unnormalized numbers (opclass 0, 2, or 3) the
23 | - For denormalized numbers (opclass 0 or 2) the number(s) is not
71 .long 0x40000000,0xc90fdaa2,0x2168c235 |pi
73 .long 0x40000000,0xc90fdaa2,0x2168c234 |pi
75 .long 0x40000000,0xc90fdaa2,0x2168c235 |pi
79 .long 0x3ffd0000,0x9a209a84,0xfbcff798 |log10(2)
80 .long 0x40000000,0xadf85458,0xa2bb4a9a |e
81 .long 0x3fff0000,0xb8aa3b29,0x5c17f0bc |log2(e)
82 .long 0x3ffd0000,0xde5bd8a9,0x37287195 |log10(e)
[all …]
/linux-3.3/include/linux/mtd/
Dndfc.h18 #define NDFC_CMD 0x00
19 #define NDFC_ALE 0x04
20 #define NDFC_DATA 0x08
21 #define NDFC_ECC 0x10
22 #define NDFC_BCFG0 0x30
23 #define NDFC_BCFG1 0x34
24 #define NDFC_BCFG2 0x38
25 #define NDFC_BCFG3 0x3c
26 #define NDFC_CCR 0x40
27 #define NDFC_STAT 0x44
[all …]
/linux-3.3/include/linux/
Drio_regs.h21 #define RIO_MAINT_SPACE_SZ 0x1000000 /* 16MB of RapidIO mainenance space */
23 #define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */
24 #define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */
25 #define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */
26 #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
27 #define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
29 #define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */
30 #define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
31 #define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
33 #define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */
[all …]

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