Lines Matching +full:0 +full:x40000000
23 #define PLX_ADDR_PLX 0x14 /* Addr PLX configuration */
24 #define PLX_ADDR_ISAC 0x18 /* Addr ISAC */
25 #define PLX_ADDR_HSCX 0x1C /* Addr HSCX */
26 #define PLX_ADDR_ALE 0x20 /* Addr ALE */
27 #define PLX_ADDR_ALEPLUS 0x24 /* Next Addr behind ALE */
29 #define PLX_SUBVEN 0x2C /* Offset SubVendor */
30 #define PLX_SUBSYS 0x2E /* Offset SubSystem */
42 volatile u_int i20VDispTop; /* Offset 0C */
57 #define sysRESET 0x01000000 /* bit 24:Softreset (Low) */
58 /* GPIO 4...0: Output fixed for our cfg! */
59 #define sysCFG 0x000000E0 /* GPIO 7,6,5: Input */
62 #define guestWAIT_CFG 0x00005555 /* 4 PCI waits for all */
63 #define guestISDN_INT_E 0x01000000 /* ISDN Int en (low) */
64 #define guestVID_INT_E 0x02000000 /* Video interrupt en (low) */
65 #define guestADI1_INT_R 0x04000000 /* ADI #1 int req (low) */
66 #define guestADI2_INT_R 0x08000000 /* ADI #2 int req (low) */
67 #define guestISDN_RES 0x10000000 /* ISDN reset bit (high) */
68 #define guestADI1_INT_S 0x20000000 /* ADI #1 int pending (low) */
69 #define guestADI2_INT_S 0x40000000 /* ADI #2 int pending (low) */
70 #define guestISDN_INT_S 0x80000000 /* ISAC int pending (low) */
72 #define g_A4T_JADE_RES 0x01000000 /* JADE Reset (High) */
73 #define g_A4T_ISAR_RES 0x02000000 /* ISAR Reset (High) */
74 #define g_A4T_ISAC_RES 0x04000000 /* ISAC Reset (High) */
75 #define g_A4T_JADE_BOOTR 0x08000000 /* JADE enable boot SRAM (Low) NOT USED */
76 #define g_A4T_ISAR_BOOTR 0x10000000 /* ISAR enable boot SRAM (Low) NOT USED */
77 #define g_A4T_JADE_INT_S 0x20000000 /* JADE interrupt pnd (Low) */
78 #define g_A4T_ISAR_INT_S 0x40000000 /* ISAR interrupt pnd (Low) */
79 #define g_A4T_ISAC_INT_S 0x80000000 /* ISAC interrupt pnd (Low) */
87 #define intISDN 0x40000000 /* GIRQ1En (ISAC/ADI) (High) */
88 #define intVID 0x20000000 /* GIRQ0En (VSYNC) (High) */
89 #define intCOD 0x10000000 /* CodRepIrqEn (High) */
90 #define intPCI 0x01000000 /* PCI IntA enable (High) */
99 #define PO_OFFSET 0x00000200 /* Postoffice offset from base */
101 #define GCS_0 0x00000000 /* Guest bus chip selects */
102 #define GCS_1 0x00100000
103 #define GCS_2 0x00200000
104 #define GCS_3 0x00300000
106 #define PO_READ 0x00000000 /* R/W from/to guest bus */
107 #define PO_WRITE 0x00800000
109 #define PO_PEND 0x02000000
117 } while (0)