48 	ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |  in nva3_copy_context_new()
53 	nv_wo32(ramin, 0xc0, 0x00190000);  in nva3_copy_context_new()
54 	nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1);  in nva3_copy_context_new()
55 	nv_wo32(ramin, 0xc8, ctx->vinst);  in nva3_copy_context_new()
56 	nv_wo32(ramin, 0xcc, 0x00000000);  in nva3_copy_context_new()
57 	nv_wo32(ramin, 0xd0, 0x00000000);  in nva3_copy_context_new()
58 	nv_wo32(ramin, 0xd4, 0x00000000);  in nva3_copy_context_new()
63 	return 0;  in nva3_copy_context_new()
86 	inst |= 0x40000000;  in nva3_copy_context_del()
89 	nv_wr32(dev, 0x104048, 0x00000000);  in nva3_copy_context_del()
91 	if (nv_rd32(dev, 0x104050) == inst)  in nva3_copy_context_del()
92 		nv_mask(dev, 0x104050, 0x40000000, 0x00000000);  in nva3_copy_context_del()
94 	if (nv_rd32(dev, 0x104054) == inst)  in nva3_copy_context_del()
95 		nv_mask(dev, 0x104054, 0x40000000, 0x00000000);  in nva3_copy_context_del()
97 	nv_wr32(dev, 0x104048, 0x00000003);  in nva3_copy_context_del()
99 	for (inst = 0xc0; inst <= 0xd4; inst += 4)  in nva3_copy_context_del()
100 		nv_wo32(chan->ramin, inst, 0x00000000);  in nva3_copy_context_del()
111 	nv50_vm_flush_engine(dev, 0x0d);  in nva3_copy_tlb_flush()
119 	nv_mask(dev, 0x000200, 0x00002000, 0x00000000);  in nva3_copy_init()
120 	nv_mask(dev, 0x000200, 0x00002000, 0x00002000);  in nva3_copy_init()
121 	nv_wr32(dev, 0x104014, 0xffffffff); /* disable all interrupts */  in nva3_copy_init()
124 	nv_wr32(dev, 0x1041c0, 0x01000000);  in nva3_copy_init()
125 	for (i = 0; i < sizeof(nva3_pcopy_data) / 4; i++)  in nva3_copy_init()
126 		nv_wr32(dev, 0x1041c4, nva3_pcopy_data[i]);  in nva3_copy_init()
128 	nv_wr32(dev, 0x104180, 0x01000000);  in nva3_copy_init()
129 	for (i = 0; i < sizeof(nva3_pcopy_code) / 4; i++) {  in nva3_copy_init()
130 		if ((i & 0x3f) == 0)  in nva3_copy_init()
131 			nv_wr32(dev, 0x104188, i >> 6);  in nva3_copy_init()
132 		nv_wr32(dev, 0x104184, nva3_pcopy_code[i]);  in nva3_copy_init()
136 	nv_wr32(dev, 0x10410c, 0x00000000);  in nva3_copy_init()
137 	nv_wr32(dev, 0x104104, 0x00000000); /* ENTRY */  in nva3_copy_init()
138 	nv_wr32(dev, 0x104100, 0x00000002); /* TRIGGER */  in nva3_copy_init()
139 	return 0;  in nva3_copy_init()
145 	nv_mask(dev, 0x104048, 0x00000003, 0x00000000);  in nva3_copy_fini()
148 	nv_wait(dev, 0x104008, 0x0000000c, 0x00000000);  in nva3_copy_fini()
149 	nv_mask(dev, 0x104054, 0x40000000, 0x00000000);  in nva3_copy_fini()
150 	nv_wr32(dev, 0x104000, 0x00000008);  in nva3_copy_fini()
151 	nv_wait(dev, 0x104008, 0x00000008, 0x00000000);  in nva3_copy_fini()
153 	nv_wr32(dev, 0x104014, 0xffffffff);  in nva3_copy_fini()
154 	return 0;  in nva3_copy_fini()
158 	{ 0x0001, "ILLEGAL_MTHD" },
159 	{ 0x0002, "INVALID_ENUM" },
160 	{ 0x0003, "INVALID_BITFIELD" },
167 	u32 dispatch = nv_rd32(dev, 0x10401c);  in nva3_copy_isr()
168 	u32 stat = nv_rd32(dev, 0x104008) & dispatch & ~(dispatch >> 16);  in nva3_copy_isr()
169 	u32 inst = nv_rd32(dev, 0x104050) & 0x3fffffff;  in nva3_copy_isr()
170 	u32 ssta = nv_rd32(dev, 0x104040) & 0x0000ffff;  in nva3_copy_isr()
171 	u32 addr = nv_rd32(dev, 0x104040) >> 16;  in nva3_copy_isr()
172 	u32 mthd = (addr & 0x07ff) << 2;  in nva3_copy_isr()
173 	u32 subc = (addr & 0x3800) >> 11;  in nva3_copy_isr()
174 	u32 data = nv_rd32(dev, 0x104044);  in nva3_copy_isr()
177 	if (stat & 0x00000040) {  in nva3_copy_isr()
180 		printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n",  in nva3_copy_isr()
182 		nv_wr32(dev, 0x104004, 0x00000040);  in nva3_copy_isr()
183 		stat &= ~0x00000040;  in nva3_copy_isr()
187 		NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);  in nva3_copy_isr()
188 		nv_wr32(dev, 0x104004, stat);  in nva3_copy_isr()
224 	NVOBJ_CLASS(dev, 0x85b5, COPY0);  in nva3_copy_create()
225 	return 0;  in nva3_copy_create()