include/asm/mmu-8xx.h

15 #define MI_GPM		0x80000000	/* Set domain manager mode */
16 #define MI_PPM		0x40000000	/* Set subpage protection */
17 #define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
18 #define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
19 #define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
20 #define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
21 #define MI_RESETVAL	0x00000000	/* Value of register at reset */
24  * Ks = 0, Kp = 1.
27 #define MI_Ks		0x80000000	/* Should not be set */
28 #define MI_Kp		0x40000000	/* Should always be set */
35 #define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
36 #define MI_EVALID	0x00000200	/* Entry is valid */
37 #define MI_ASIDMASK	0x0000000f	/* ASID match value */
45 #define MI_APG		0x000001e0	/* Access protection group (0) */
46 #define MI_GUARDED	0x00000010	/* Guarded storage */
47 #define MI_PSMASK	0x0000000c	/* Mask of page size bits */
48 #define MI_PS8MEG	0x0000000c	/* 8M page size */
49 #define MI_PS512K	0x00000004	/* 512K page size */
50 #define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
51 #define MI_SVALID	0x00000001	/* Segment entry is valid */
61  * pages for boot initialization.  This has real page number of 0,
65 #define MI_BOOTINIT	0x000001fd
68 #define MD_GPM		0x80000000	/* Set domain manager mode */
69 #define MD_PPM		0x40000000	/* Set subpage protection */
70 #define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
71 #define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
72 #define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
73 #define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
74 #define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
75 #define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
76 #define MD_RESETVAL	0x04000000	/* Value of register at reset */
79 #define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
83  * Ks = 0, Kp = 1.
86 #define MD_Ks		0x80000000	/* Should not be set */
87 #define MD_Kp		0x40000000	/* Should always be set */
94 #define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
95 #define MD_EVALID	0x00000200	/* Entry is valid */
96 #define MD_ASIDMASK	0x0000000f	/* ASID match value */
104 #define	M_L1TB		0xfffff000	/* Level 1 table base address */
105 #define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
114 #define MD_L2TB		0xfffff000	/* Level 2 table base address */
115 #define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
116 #define MD_APG		0x000001e0	/* Access protection group (0) */
117 #define MD_GUARDED	0x00000010	/* Guarded storage */
118 #define MD_PSMASK	0x0000000c	/* Mask of page size bits */
119 #define MD_PS8MEG	0x0000000c	/* 8M page size */
120 #define MD_PS512K	0x00000004	/* 512K page size */
121 #define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
122 #define MD_WT		0x00000002	/* Use writethrough page attribute */
123 #define MD_SVALID	0x00000001	/* Segment entry is valid */