Lines Matching +full:0 +full:x40000000
10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
54 return 0; in nv20_graph_unload_context()
63 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); in nv20_graph_unload_context()
64 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; in nv20_graph_unload_context()
67 return 0; in nv20_graph_unload_context()
75 uint32_t rdi_index = 0x2c80000; in nv20_graph_rdi()
77 if (dev_priv->chipset == 0x20) { in nv20_graph_rdi()
78 rdi_index = 0x3d0000; in nv20_graph_rdi()
83 for (i = 0; i < writecount; i++) in nv20_graph_rdi()
84 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0); in nv20_graph_rdi()
94 nv_wo32(ctx, 0x033c, 0xffff0000); in nv20_graph_context_init()
95 nv_wo32(ctx, 0x03a0, 0x0fff0000); in nv20_graph_context_init()
96 nv_wo32(ctx, 0x03a4, 0x0fff0000); in nv20_graph_context_init()
97 nv_wo32(ctx, 0x047c, 0x00000101); in nv20_graph_context_init()
98 nv_wo32(ctx, 0x0490, 0x00000111); in nv20_graph_context_init()
99 nv_wo32(ctx, 0x04a8, 0x44400000); in nv20_graph_context_init()
100 for (i = 0x04d4; i <= 0x04e0; i += 4) in nv20_graph_context_init()
101 nv_wo32(ctx, i, 0x00030303); in nv20_graph_context_init()
102 for (i = 0x04f4; i <= 0x0500; i += 4) in nv20_graph_context_init()
103 nv_wo32(ctx, i, 0x00080000); in nv20_graph_context_init()
104 for (i = 0x050c; i <= 0x0518; i += 4) in nv20_graph_context_init()
105 nv_wo32(ctx, i, 0x01012000); in nv20_graph_context_init()
106 for (i = 0x051c; i <= 0x0528; i += 4) in nv20_graph_context_init()
107 nv_wo32(ctx, i, 0x000105b8); in nv20_graph_context_init()
108 for (i = 0x052c; i <= 0x0538; i += 4) in nv20_graph_context_init()
109 nv_wo32(ctx, i, 0x00080008); in nv20_graph_context_init()
110 for (i = 0x055c; i <= 0x0598; i += 4) in nv20_graph_context_init()
111 nv_wo32(ctx, i, 0x07ff0000); in nv20_graph_context_init()
112 nv_wo32(ctx, 0x05a4, 0x4b7fffff); in nv20_graph_context_init()
113 nv_wo32(ctx, 0x05fc, 0x00000001); in nv20_graph_context_init()
114 nv_wo32(ctx, 0x0604, 0x00004000); in nv20_graph_context_init()
115 nv_wo32(ctx, 0x0610, 0x00000001); in nv20_graph_context_init()
116 nv_wo32(ctx, 0x0618, 0x00040000); in nv20_graph_context_init()
117 nv_wo32(ctx, 0x061c, 0x00010000); in nv20_graph_context_init()
118 for (i = 0x1c1c; i <= 0x248c; i += 16) { in nv20_graph_context_init()
119 nv_wo32(ctx, (i + 0), 0x10700ff9); in nv20_graph_context_init()
120 nv_wo32(ctx, (i + 4), 0x0436086c); in nv20_graph_context_init()
121 nv_wo32(ctx, (i + 8), 0x000c001b); in nv20_graph_context_init()
123 nv_wo32(ctx, 0x281c, 0x3f800000); in nv20_graph_context_init()
124 nv_wo32(ctx, 0x2830, 0x3f800000); in nv20_graph_context_init()
125 nv_wo32(ctx, 0x285c, 0x40000000); in nv20_graph_context_init()
126 nv_wo32(ctx, 0x2860, 0x3f800000); in nv20_graph_context_init()
127 nv_wo32(ctx, 0x2864, 0x3f000000); in nv20_graph_context_init()
128 nv_wo32(ctx, 0x286c, 0x40000000); in nv20_graph_context_init()
129 nv_wo32(ctx, 0x2870, 0x3f800000); in nv20_graph_context_init()
130 nv_wo32(ctx, 0x2878, 0xbf800000); in nv20_graph_context_init()
131 nv_wo32(ctx, 0x2880, 0xbf800000); in nv20_graph_context_init()
132 nv_wo32(ctx, 0x34a4, 0x000fe000); in nv20_graph_context_init()
133 nv_wo32(ctx, 0x3530, 0x000003f8); in nv20_graph_context_init()
134 nv_wo32(ctx, 0x3540, 0x002fe000); in nv20_graph_context_init()
135 for (i = 0x355c; i <= 0x3578; i += 4) in nv20_graph_context_init()
136 nv_wo32(ctx, i, 0x001c527c); in nv20_graph_context_init()
144 nv_wo32(ctx, 0x035c, 0xffff0000); in nv25_graph_context_init()
145 nv_wo32(ctx, 0x03c0, 0x0fff0000); in nv25_graph_context_init()
146 nv_wo32(ctx, 0x03c4, 0x0fff0000); in nv25_graph_context_init()
147 nv_wo32(ctx, 0x049c, 0x00000101); in nv25_graph_context_init()
148 nv_wo32(ctx, 0x04b0, 0x00000111); in nv25_graph_context_init()
149 nv_wo32(ctx, 0x04c8, 0x00000080); in nv25_graph_context_init()
150 nv_wo32(ctx, 0x04cc, 0xffff0000); in nv25_graph_context_init()
151 nv_wo32(ctx, 0x04d0, 0x00000001); in nv25_graph_context_init()
152 nv_wo32(ctx, 0x04e4, 0x44400000); in nv25_graph_context_init()
153 nv_wo32(ctx, 0x04fc, 0x4b800000); in nv25_graph_context_init()
154 for (i = 0x0510; i <= 0x051c; i += 4) in nv25_graph_context_init()
155 nv_wo32(ctx, i, 0x00030303); in nv25_graph_context_init()
156 for (i = 0x0530; i <= 0x053c; i += 4) in nv25_graph_context_init()
157 nv_wo32(ctx, i, 0x00080000); in nv25_graph_context_init()
158 for (i = 0x0548; i <= 0x0554; i += 4) in nv25_graph_context_init()
159 nv_wo32(ctx, i, 0x01012000); in nv25_graph_context_init()
160 for (i = 0x0558; i <= 0x0564; i += 4) in nv25_graph_context_init()
161 nv_wo32(ctx, i, 0x000105b8); in nv25_graph_context_init()
162 for (i = 0x0568; i <= 0x0574; i += 4) in nv25_graph_context_init()
163 nv_wo32(ctx, i, 0x00080008); in nv25_graph_context_init()
164 for (i = 0x0598; i <= 0x05d4; i += 4) in nv25_graph_context_init()
165 nv_wo32(ctx, i, 0x07ff0000); in nv25_graph_context_init()
166 nv_wo32(ctx, 0x05e0, 0x4b7fffff); in nv25_graph_context_init()
167 nv_wo32(ctx, 0x0620, 0x00000080); in nv25_graph_context_init()
168 nv_wo32(ctx, 0x0624, 0x30201000); in nv25_graph_context_init()
169 nv_wo32(ctx, 0x0628, 0x70605040); in nv25_graph_context_init()
170 nv_wo32(ctx, 0x062c, 0xb0a09080); in nv25_graph_context_init()
171 nv_wo32(ctx, 0x0630, 0xf0e0d0c0); in nv25_graph_context_init()
172 nv_wo32(ctx, 0x0664, 0x00000001); in nv25_graph_context_init()
173 nv_wo32(ctx, 0x066c, 0x00004000); in nv25_graph_context_init()
174 nv_wo32(ctx, 0x0678, 0x00000001); in nv25_graph_context_init()
175 nv_wo32(ctx, 0x0680, 0x00040000); in nv25_graph_context_init()
176 nv_wo32(ctx, 0x0684, 0x00010000); in nv25_graph_context_init()
177 for (i = 0x1b04; i <= 0x2374; i += 16) { in nv25_graph_context_init()
178 nv_wo32(ctx, (i + 0), 0x10700ff9); in nv25_graph_context_init()
179 nv_wo32(ctx, (i + 4), 0x0436086c); in nv25_graph_context_init()
180 nv_wo32(ctx, (i + 8), 0x000c001b); in nv25_graph_context_init()
182 nv_wo32(ctx, 0x2704, 0x3f800000); in nv25_graph_context_init()
183 nv_wo32(ctx, 0x2718, 0x3f800000); in nv25_graph_context_init()
184 nv_wo32(ctx, 0x2744, 0x40000000); in nv25_graph_context_init()
185 nv_wo32(ctx, 0x2748, 0x3f800000); in nv25_graph_context_init()
186 nv_wo32(ctx, 0x274c, 0x3f000000); in nv25_graph_context_init()
187 nv_wo32(ctx, 0x2754, 0x40000000); in nv25_graph_context_init()
188 nv_wo32(ctx, 0x2758, 0x3f800000); in nv25_graph_context_init()
189 nv_wo32(ctx, 0x2760, 0xbf800000); in nv25_graph_context_init()
190 nv_wo32(ctx, 0x2768, 0xbf800000); in nv25_graph_context_init()
191 nv_wo32(ctx, 0x308c, 0x000fe000); in nv25_graph_context_init()
192 nv_wo32(ctx, 0x3108, 0x000003f8); in nv25_graph_context_init()
193 nv_wo32(ctx, 0x3468, 0x002fe000); in nv25_graph_context_init()
194 for (i = 0x3484; i <= 0x34a0; i += 4) in nv25_graph_context_init()
195 nv_wo32(ctx, i, 0x001c527c); in nv25_graph_context_init()
203 nv_wo32(ctx, 0x033c, 0xffff0000); in nv2a_graph_context_init()
204 nv_wo32(ctx, 0x03a0, 0x0fff0000); in nv2a_graph_context_init()
205 nv_wo32(ctx, 0x03a4, 0x0fff0000); in nv2a_graph_context_init()
206 nv_wo32(ctx, 0x047c, 0x00000101); in nv2a_graph_context_init()
207 nv_wo32(ctx, 0x0490, 0x00000111); in nv2a_graph_context_init()
208 nv_wo32(ctx, 0x04a8, 0x44400000); in nv2a_graph_context_init()
209 for (i = 0x04d4; i <= 0x04e0; i += 4) in nv2a_graph_context_init()
210 nv_wo32(ctx, i, 0x00030303); in nv2a_graph_context_init()
211 for (i = 0x04f4; i <= 0x0500; i += 4) in nv2a_graph_context_init()
212 nv_wo32(ctx, i, 0x00080000); in nv2a_graph_context_init()
213 for (i = 0x050c; i <= 0x0518; i += 4) in nv2a_graph_context_init()
214 nv_wo32(ctx, i, 0x01012000); in nv2a_graph_context_init()
215 for (i = 0x051c; i <= 0x0528; i += 4) in nv2a_graph_context_init()
216 nv_wo32(ctx, i, 0x000105b8); in nv2a_graph_context_init()
217 for (i = 0x052c; i <= 0x0538; i += 4) in nv2a_graph_context_init()
218 nv_wo32(ctx, i, 0x00080008); in nv2a_graph_context_init()
219 for (i = 0x055c; i <= 0x0598; i += 4) in nv2a_graph_context_init()
220 nv_wo32(ctx, i, 0x07ff0000); in nv2a_graph_context_init()
221 nv_wo32(ctx, 0x05a4, 0x4b7fffff); in nv2a_graph_context_init()
222 nv_wo32(ctx, 0x05fc, 0x00000001); in nv2a_graph_context_init()
223 nv_wo32(ctx, 0x0604, 0x00004000); in nv2a_graph_context_init()
224 nv_wo32(ctx, 0x0610, 0x00000001); in nv2a_graph_context_init()
225 nv_wo32(ctx, 0x0618, 0x00040000); in nv2a_graph_context_init()
226 nv_wo32(ctx, 0x061c, 0x00010000); in nv2a_graph_context_init()
227 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ in nv2a_graph_context_init()
228 nv_wo32(ctx, (i + 0), 0x10700ff9); in nv2a_graph_context_init()
229 nv_wo32(ctx, (i + 4), 0x0436086c); in nv2a_graph_context_init()
230 nv_wo32(ctx, (i + 8), 0x000c001b); in nv2a_graph_context_init()
232 nv_wo32(ctx, 0x269c, 0x3f800000); in nv2a_graph_context_init()
233 nv_wo32(ctx, 0x26b0, 0x3f800000); in nv2a_graph_context_init()
234 nv_wo32(ctx, 0x26dc, 0x40000000); in nv2a_graph_context_init()
235 nv_wo32(ctx, 0x26e0, 0x3f800000); in nv2a_graph_context_init()
236 nv_wo32(ctx, 0x26e4, 0x3f000000); in nv2a_graph_context_init()
237 nv_wo32(ctx, 0x26ec, 0x40000000); in nv2a_graph_context_init()
238 nv_wo32(ctx, 0x26f0, 0x3f800000); in nv2a_graph_context_init()
239 nv_wo32(ctx, 0x26f8, 0xbf800000); in nv2a_graph_context_init()
240 nv_wo32(ctx, 0x2700, 0xbf800000); in nv2a_graph_context_init()
241 nv_wo32(ctx, 0x3024, 0x000fe000); in nv2a_graph_context_init()
242 nv_wo32(ctx, 0x30a0, 0x000003f8); in nv2a_graph_context_init()
243 nv_wo32(ctx, 0x33fc, 0x002fe000); in nv2a_graph_context_init()
244 for (i = 0x341c; i <= 0x3438; i += 4) in nv2a_graph_context_init()
245 nv_wo32(ctx, i, 0x001c527c); in nv2a_graph_context_init()
253 nv_wo32(ctx, 0x0410, 0x00000101); in nv30_31_graph_context_init()
254 nv_wo32(ctx, 0x0424, 0x00000111); in nv30_31_graph_context_init()
255 nv_wo32(ctx, 0x0428, 0x00000060); in nv30_31_graph_context_init()
256 nv_wo32(ctx, 0x0444, 0x00000080); in nv30_31_graph_context_init()
257 nv_wo32(ctx, 0x0448, 0xffff0000); in nv30_31_graph_context_init()
258 nv_wo32(ctx, 0x044c, 0x00000001); in nv30_31_graph_context_init()
259 nv_wo32(ctx, 0x0460, 0x44400000); in nv30_31_graph_context_init()
260 nv_wo32(ctx, 0x048c, 0xffff0000); in nv30_31_graph_context_init()
261 for (i = 0x04e0; i < 0x04e8; i += 4) in nv30_31_graph_context_init()
262 nv_wo32(ctx, i, 0x0fff0000); in nv30_31_graph_context_init()
263 nv_wo32(ctx, 0x04ec, 0x00011100); in nv30_31_graph_context_init()
264 for (i = 0x0508; i < 0x0548; i += 4) in nv30_31_graph_context_init()
265 nv_wo32(ctx, i, 0x07ff0000); in nv30_31_graph_context_init()
266 nv_wo32(ctx, 0x0550, 0x4b7fffff); in nv30_31_graph_context_init()
267 nv_wo32(ctx, 0x058c, 0x00000080); in nv30_31_graph_context_init()
268 nv_wo32(ctx, 0x0590, 0x30201000); in nv30_31_graph_context_init()
269 nv_wo32(ctx, 0x0594, 0x70605040); in nv30_31_graph_context_init()
270 nv_wo32(ctx, 0x0598, 0xb8a89888); in nv30_31_graph_context_init()
271 nv_wo32(ctx, 0x059c, 0xf8e8d8c8); in nv30_31_graph_context_init()
272 nv_wo32(ctx, 0x05b0, 0xb0000000); in nv30_31_graph_context_init()
273 for (i = 0x0600; i < 0x0640; i += 4) in nv30_31_graph_context_init()
274 nv_wo32(ctx, i, 0x00010588); in nv30_31_graph_context_init()
275 for (i = 0x0640; i < 0x0680; i += 4) in nv30_31_graph_context_init()
276 nv_wo32(ctx, i, 0x00030303); in nv30_31_graph_context_init()
277 for (i = 0x06c0; i < 0x0700; i += 4) in nv30_31_graph_context_init()
278 nv_wo32(ctx, i, 0x0008aae4); in nv30_31_graph_context_init()
279 for (i = 0x0700; i < 0x0740; i += 4) in nv30_31_graph_context_init()
280 nv_wo32(ctx, i, 0x01012000); in nv30_31_graph_context_init()
281 for (i = 0x0740; i < 0x0780; i += 4) in nv30_31_graph_context_init()
282 nv_wo32(ctx, i, 0x00080008); in nv30_31_graph_context_init()
283 nv_wo32(ctx, 0x085c, 0x00040000); in nv30_31_graph_context_init()
284 nv_wo32(ctx, 0x0860, 0x00010000); in nv30_31_graph_context_init()
285 for (i = 0x0864; i < 0x0874; i += 4) in nv30_31_graph_context_init()
286 nv_wo32(ctx, i, 0x00040004); in nv30_31_graph_context_init()
287 for (i = 0x1f18; i <= 0x3088 ; i += 16) { in nv30_31_graph_context_init()
288 nv_wo32(ctx, i + 0, 0x10700ff9); in nv30_31_graph_context_init()
289 nv_wo32(ctx, i + 1, 0x0436086c); in nv30_31_graph_context_init()
290 nv_wo32(ctx, i + 2, 0x000c001b); in nv30_31_graph_context_init()
292 for (i = 0x30b8; i < 0x30c8; i += 4) in nv30_31_graph_context_init()
293 nv_wo32(ctx, i, 0x0000ffff); in nv30_31_graph_context_init()
294 nv_wo32(ctx, 0x344c, 0x3f800000); in nv30_31_graph_context_init()
295 nv_wo32(ctx, 0x3808, 0x3f800000); in nv30_31_graph_context_init()
296 nv_wo32(ctx, 0x381c, 0x3f800000); in nv30_31_graph_context_init()
297 nv_wo32(ctx, 0x3848, 0x40000000); in nv30_31_graph_context_init()
298 nv_wo32(ctx, 0x384c, 0x3f800000); in nv30_31_graph_context_init()
299 nv_wo32(ctx, 0x3850, 0x3f000000); in nv30_31_graph_context_init()
300 nv_wo32(ctx, 0x3858, 0x40000000); in nv30_31_graph_context_init()
301 nv_wo32(ctx, 0x385c, 0x3f800000); in nv30_31_graph_context_init()
302 nv_wo32(ctx, 0x3864, 0xbf800000); in nv30_31_graph_context_init()
303 nv_wo32(ctx, 0x386c, 0xbf800000); in nv30_31_graph_context_init()
311 nv_wo32(ctx, 0x040c, 0x01000101); in nv34_graph_context_init()
312 nv_wo32(ctx, 0x0420, 0x00000111); in nv34_graph_context_init()
313 nv_wo32(ctx, 0x0424, 0x00000060); in nv34_graph_context_init()
314 nv_wo32(ctx, 0x0440, 0x00000080); in nv34_graph_context_init()
315 nv_wo32(ctx, 0x0444, 0xffff0000); in nv34_graph_context_init()
316 nv_wo32(ctx, 0x0448, 0x00000001); in nv34_graph_context_init()
317 nv_wo32(ctx, 0x045c, 0x44400000); in nv34_graph_context_init()
318 nv_wo32(ctx, 0x0480, 0xffff0000); in nv34_graph_context_init()
319 for (i = 0x04d4; i < 0x04dc; i += 4) in nv34_graph_context_init()
320 nv_wo32(ctx, i, 0x0fff0000); in nv34_graph_context_init()
321 nv_wo32(ctx, 0x04e0, 0x00011100); in nv34_graph_context_init()
322 for (i = 0x04fc; i < 0x053c; i += 4) in nv34_graph_context_init()
323 nv_wo32(ctx, i, 0x07ff0000); in nv34_graph_context_init()
324 nv_wo32(ctx, 0x0544, 0x4b7fffff); in nv34_graph_context_init()
325 nv_wo32(ctx, 0x057c, 0x00000080); in nv34_graph_context_init()
326 nv_wo32(ctx, 0x0580, 0x30201000); in nv34_graph_context_init()
327 nv_wo32(ctx, 0x0584, 0x70605040); in nv34_graph_context_init()
328 nv_wo32(ctx, 0x0588, 0xb8a89888); in nv34_graph_context_init()
329 nv_wo32(ctx, 0x058c, 0xf8e8d8c8); in nv34_graph_context_init()
330 nv_wo32(ctx, 0x05a0, 0xb0000000); in nv34_graph_context_init()
331 for (i = 0x05f0; i < 0x0630; i += 4) in nv34_graph_context_init()
332 nv_wo32(ctx, i, 0x00010588); in nv34_graph_context_init()
333 for (i = 0x0630; i < 0x0670; i += 4) in nv34_graph_context_init()
334 nv_wo32(ctx, i, 0x00030303); in nv34_graph_context_init()
335 for (i = 0x06b0; i < 0x06f0; i += 4) in nv34_graph_context_init()
336 nv_wo32(ctx, i, 0x0008aae4); in nv34_graph_context_init()
337 for (i = 0x06f0; i < 0x0730; i += 4) in nv34_graph_context_init()
338 nv_wo32(ctx, i, 0x01012000); in nv34_graph_context_init()
339 for (i = 0x0730; i < 0x0770; i += 4) in nv34_graph_context_init()
340 nv_wo32(ctx, i, 0x00080008); in nv34_graph_context_init()
341 nv_wo32(ctx, 0x0850, 0x00040000); in nv34_graph_context_init()
342 nv_wo32(ctx, 0x0854, 0x00010000); in nv34_graph_context_init()
343 for (i = 0x0858; i < 0x0868; i += 4) in nv34_graph_context_init()
344 nv_wo32(ctx, i, 0x00040004); in nv34_graph_context_init()
345 for (i = 0x15ac; i <= 0x271c ; i += 16) { in nv34_graph_context_init()
346 nv_wo32(ctx, i + 0, 0x10700ff9); in nv34_graph_context_init()
347 nv_wo32(ctx, i + 1, 0x0436086c); in nv34_graph_context_init()
348 nv_wo32(ctx, i + 2, 0x000c001b); in nv34_graph_context_init()
350 for (i = 0x274c; i < 0x275c; i += 4) in nv34_graph_context_init()
351 nv_wo32(ctx, i, 0x0000ffff); in nv34_graph_context_init()
352 nv_wo32(ctx, 0x2ae0, 0x3f800000); in nv34_graph_context_init()
353 nv_wo32(ctx, 0x2e9c, 0x3f800000); in nv34_graph_context_init()
354 nv_wo32(ctx, 0x2eb0, 0x3f800000); in nv34_graph_context_init()
355 nv_wo32(ctx, 0x2edc, 0x40000000); in nv34_graph_context_init()
356 nv_wo32(ctx, 0x2ee0, 0x3f800000); in nv34_graph_context_init()
357 nv_wo32(ctx, 0x2ee4, 0x3f000000); in nv34_graph_context_init()
358 nv_wo32(ctx, 0x2eec, 0x40000000); in nv34_graph_context_init()
359 nv_wo32(ctx, 0x2ef0, 0x3f800000); in nv34_graph_context_init()
360 nv_wo32(ctx, 0x2ef8, 0xbf800000); in nv34_graph_context_init()
361 nv_wo32(ctx, 0x2f00, 0xbf800000); in nv34_graph_context_init()
369 nv_wo32(ctx, 0x040c, 0x00000101); in nv35_36_graph_context_init()
370 nv_wo32(ctx, 0x0420, 0x00000111); in nv35_36_graph_context_init()
371 nv_wo32(ctx, 0x0424, 0x00000060); in nv35_36_graph_context_init()
372 nv_wo32(ctx, 0x0440, 0x00000080); in nv35_36_graph_context_init()
373 nv_wo32(ctx, 0x0444, 0xffff0000); in nv35_36_graph_context_init()
374 nv_wo32(ctx, 0x0448, 0x00000001); in nv35_36_graph_context_init()
375 nv_wo32(ctx, 0x045c, 0x44400000); in nv35_36_graph_context_init()
376 nv_wo32(ctx, 0x0488, 0xffff0000); in nv35_36_graph_context_init()
377 for (i = 0x04dc; i < 0x04e4; i += 4) in nv35_36_graph_context_init()
378 nv_wo32(ctx, i, 0x0fff0000); in nv35_36_graph_context_init()
379 nv_wo32(ctx, 0x04e8, 0x00011100); in nv35_36_graph_context_init()
380 for (i = 0x0504; i < 0x0544; i += 4) in nv35_36_graph_context_init()
381 nv_wo32(ctx, i, 0x07ff0000); in nv35_36_graph_context_init()
382 nv_wo32(ctx, 0x054c, 0x4b7fffff); in nv35_36_graph_context_init()
383 nv_wo32(ctx, 0x0588, 0x00000080); in nv35_36_graph_context_init()
384 nv_wo32(ctx, 0x058c, 0x30201000); in nv35_36_graph_context_init()
385 nv_wo32(ctx, 0x0590, 0x70605040); in nv35_36_graph_context_init()
386 nv_wo32(ctx, 0x0594, 0xb8a89888); in nv35_36_graph_context_init()
387 nv_wo32(ctx, 0x0598, 0xf8e8d8c8); in nv35_36_graph_context_init()
388 nv_wo32(ctx, 0x05ac, 0xb0000000); in nv35_36_graph_context_init()
389 for (i = 0x0604; i < 0x0644; i += 4) in nv35_36_graph_context_init()
390 nv_wo32(ctx, i, 0x00010588); in nv35_36_graph_context_init()
391 for (i = 0x0644; i < 0x0684; i += 4) in nv35_36_graph_context_init()
392 nv_wo32(ctx, i, 0x00030303); in nv35_36_graph_context_init()
393 for (i = 0x06c4; i < 0x0704; i += 4) in nv35_36_graph_context_init()
394 nv_wo32(ctx, i, 0x0008aae4); in nv35_36_graph_context_init()
395 for (i = 0x0704; i < 0x0744; i += 4) in nv35_36_graph_context_init()
396 nv_wo32(ctx, i, 0x01012000); in nv35_36_graph_context_init()
397 for (i = 0x0744; i < 0x0784; i += 4) in nv35_36_graph_context_init()
398 nv_wo32(ctx, i, 0x00080008); in nv35_36_graph_context_init()
399 nv_wo32(ctx, 0x0860, 0x00040000); in nv35_36_graph_context_init()
400 nv_wo32(ctx, 0x0864, 0x00010000); in nv35_36_graph_context_init()
401 for (i = 0x0868; i < 0x0878; i += 4) in nv35_36_graph_context_init()
402 nv_wo32(ctx, i, 0x00040004); in nv35_36_graph_context_init()
403 for (i = 0x1f1c; i <= 0x308c ; i += 16) { in nv35_36_graph_context_init()
404 nv_wo32(ctx, i + 0, 0x10700ff9); in nv35_36_graph_context_init()
405 nv_wo32(ctx, i + 4, 0x0436086c); in nv35_36_graph_context_init()
406 nv_wo32(ctx, i + 8, 0x000c001b); in nv35_36_graph_context_init()
408 for (i = 0x30bc; i < 0x30cc; i += 4) in nv35_36_graph_context_init()
409 nv_wo32(ctx, i, 0x0000ffff); in nv35_36_graph_context_init()
410 nv_wo32(ctx, 0x3450, 0x3f800000); in nv35_36_graph_context_init()
411 nv_wo32(ctx, 0x380c, 0x3f800000); in nv35_36_graph_context_init()
412 nv_wo32(ctx, 0x3820, 0x3f800000); in nv35_36_graph_context_init()
413 nv_wo32(ctx, 0x384c, 0x40000000); in nv35_36_graph_context_init()
414 nv_wo32(ctx, 0x3850, 0x3f800000); in nv35_36_graph_context_init()
415 nv_wo32(ctx, 0x3854, 0x3f000000); in nv35_36_graph_context_init()
416 nv_wo32(ctx, 0x385c, 0x40000000); in nv35_36_graph_context_init()
417 nv_wo32(ctx, 0x3860, 0x3f800000); in nv35_36_graph_context_init()
418 nv_wo32(ctx, 0x3868, 0xbf800000); in nv35_36_graph_context_init()
419 nv_wo32(ctx, 0x3870, 0xbf800000); in nv35_36_graph_context_init()
440 nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1); in nv20_graph_context_new()
444 return 0; in nv20_graph_context_new()
457 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv20_graph_context_del()
463 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv20_graph_context_del()
467 nv_wo32(pgraph->ctxtab, chan->id * 4, 0); in nv20_graph_context_del()
483 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_graph_set_tile_region()
485 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_graph_set_tile_region()
487 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); in nv20_graph_set_tile_region()
492 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); in nv20_graph_set_tile_region()
514 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv20_graph_init()
515 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv20_graph_init()
517 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv20_graph_init()
518 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv20_graph_init()
519 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700); in nv20_graph_init()
520 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ in nv20_graph_init()
521 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); in nv20_graph_init()
522 nv_wr32(dev, 0x40009C , 0x00000040); in nv20_graph_init()
524 if (dev_priv->chipset >= 0x25) { in nv20_graph_init()
525 nv_wr32(dev, 0x400890, 0x00a8cfff); in nv20_graph_init()
526 nv_wr32(dev, 0x400610, 0x304B1FB6); in nv20_graph_init()
527 nv_wr32(dev, 0x400B80, 0x1cbd3883); in nv20_graph_init()
528 nv_wr32(dev, 0x400B84, 0x44000000); in nv20_graph_init()
529 nv_wr32(dev, 0x400098, 0x40000080); in nv20_graph_init()
530 nv_wr32(dev, 0x400B88, 0x000000ff); in nv20_graph_init()
533 nv_wr32(dev, 0x400880, 0x0008c7df); in nv20_graph_init()
534 nv_wr32(dev, 0x400094, 0x00000005); in nv20_graph_init()
535 nv_wr32(dev, 0x400B80, 0x45eae20e); in nv20_graph_init()
536 nv_wr32(dev, 0x400B84, 0x24000000); in nv20_graph_init()
537 nv_wr32(dev, 0x400098, 0x00000040); in nv20_graph_init()
538 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038); in nv20_graph_init()
539 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); in nv20_graph_init()
540 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038); in nv20_graph_init()
541 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); in nv20_graph_init()
545 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) in nv20_graph_init()
548 nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324)); in nv20_graph_init()
549 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); in nv20_graph_init()
550 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324)); in nv20_graph_init()
552 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); in nv20_graph_init()
553 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv20_graph_init()
555 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00; in nv20_graph_init()
557 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100; in nv20_graph_init()
561 vramsz = pci_resource_len(dev->pdev, 0) - 1; in nv20_graph_init()
562 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); in nv20_graph_init()
563 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); in nv20_graph_init()
564 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); in nv20_graph_init()
566 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); in nv20_graph_init()
568 nv_wr32(dev, 0x400820, 0); in nv20_graph_init()
569 nv_wr32(dev, 0x400824, 0); in nv20_graph_init()
570 nv_wr32(dev, 0x400864, vramsz - 1); in nv20_graph_init()
571 nv_wr32(dev, 0x400868, vramsz - 1); in nv20_graph_init()
574 nv_wr32(dev, 0x400B20, 0x00000000); in nv20_graph_init()
575 nv_wr32(dev, 0x400B04, 0xFFFFFFFF); in nv20_graph_init()
577 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); in nv20_graph_init()
578 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); in nv20_graph_init()
579 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); in nv20_graph_init()
580 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); in nv20_graph_init()
582 return 0; in nv20_graph_init()
599 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv30_graph_init()
600 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv30_graph_init()
602 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv30_graph_init()
603 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv30_graph_init()
604 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv30_graph_init()
605 nv_wr32(dev, 0x400890, 0x01b463ff); in nv30_graph_init()
606 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475); in nv30_graph_init()
607 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv30_graph_init()
608 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); in nv30_graph_init()
609 nv_wr32(dev, 0x400B80, 0x1003d888); in nv30_graph_init()
610 nv_wr32(dev, 0x400B84, 0x0c000000); in nv30_graph_init()
611 nv_wr32(dev, 0x400098, 0x00000000); in nv30_graph_init()
612 nv_wr32(dev, 0x40009C, 0x0005ad00); in nv30_graph_init()
613 nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ in nv30_graph_init()
614 nv_wr32(dev, 0x4000a0, 0x00000000); in nv30_graph_init()
615 nv_wr32(dev, 0x4000a4, 0x00000008); in nv30_graph_init()
616 nv_wr32(dev, 0x4008a8, 0xb784a400); in nv30_graph_init()
617 nv_wr32(dev, 0x400ba0, 0x002f8685); in nv30_graph_init()
618 nv_wr32(dev, 0x400ba4, 0x00231f3f); in nv30_graph_init()
619 nv_wr32(dev, 0x4008a4, 0x40000020); in nv30_graph_init()
621 if (dev_priv->chipset == 0x34) { in nv30_graph_init()
622 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); in nv30_graph_init()
623 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201); in nv30_graph_init()
624 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); in nv30_graph_init()
625 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008); in nv30_graph_init()
626 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); in nv30_graph_init()
627 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032); in nv30_graph_init()
628 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004); in nv30_graph_init()
629 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002); in nv30_graph_init()
632 nv_wr32(dev, 0x4000c0, 0x00000016); in nv30_graph_init()
635 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) in nv30_graph_init()
638 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); in nv30_graph_init()
639 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); in nv30_graph_init()
640 nv_wr32(dev, 0x0040075c , 0x00000001); in nv30_graph_init()
643 /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */ in nv30_graph_init()
644 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); in nv30_graph_init()
645 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); in nv30_graph_init()
646 if (dev_priv->chipset != 0x34) { in nv30_graph_init()
647 nv_wr32(dev, 0x400750, 0x00EA0000); in nv30_graph_init()
648 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0)); in nv30_graph_init()
649 nv_wr32(dev, 0x400750, 0x00EA0004); in nv30_graph_init()
650 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1)); in nv30_graph_init()
653 return 0; in nv30_graph_init()
659 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); in nv20_graph_fini()
660 if (!nv_wait(dev, NV04_PGRAPH_STATUS, ~0, 0) && suspend) { in nv20_graph_fini()
661 nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); in nv20_graph_fini()
665 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000); in nv20_graph_fini()
666 return 0; in nv20_graph_fini()
678 u32 chid = (addr & 0x01f00000) >> 20; in nv20_graph_isr()
679 u32 subc = (addr & 0x00070000) >> 16; in nv20_graph_isr()
680 u32 mthd = (addr & 0x00001ffc); in nv20_graph_isr()
682 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff; in nv20_graph_isr()
693 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001); in nv20_graph_isr()
703 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x " in nv20_graph_isr()
704 "mthd 0x%04x data 0x%08x\n", in nv20_graph_isr()
740 pgraph->grctx_user = 0x0028; in nv20_graph_create()
744 case 0x20: in nv20_graph_create()
747 pgraph->grctx_user = 0x0000; in nv20_graph_create()
749 case 0x25: in nv20_graph_create()
750 case 0x28: in nv20_graph_create()
754 case 0x2a: in nv20_graph_create()
757 pgraph->grctx_user = 0x0000; in nv20_graph_create()
762 return 0; in nv20_graph_create()
767 case 0x30: in nv20_graph_create()
768 case 0x31: in nv20_graph_create()
772 case 0x34: in nv20_graph_create()
776 case 0x35: in nv20_graph_create()
777 case 0x36: in nv20_graph_create()
784 return 0; in nv20_graph_create()
800 NVOBJ_CLASS(dev, 0x506e, SW); in nv20_graph_create()
801 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip); in nv20_graph_create()
803 NVOBJ_CLASS(dev, 0x0030, GR); /* null */ in nv20_graph_create()
804 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */ in nv20_graph_create()
805 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */ in nv20_graph_create()
806 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */ in nv20_graph_create()
807 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */ in nv20_graph_create()
808 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */ in nv20_graph_create()
809 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */ in nv20_graph_create()
810 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */ in nv20_graph_create()
811 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */ in nv20_graph_create()
812 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */ in nv20_graph_create()
813 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */ in nv20_graph_create()
814 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */ in nv20_graph_create()
816 NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */ in nv20_graph_create()
817 NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */ in nv20_graph_create()
820 if (dev_priv->chipset < 0x25) in nv20_graph_create()
821 NVOBJ_CLASS(dev, 0x0097, GR); in nv20_graph_create()
823 NVOBJ_CLASS(dev, 0x0597, GR); in nv20_graph_create()
825 NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */ in nv20_graph_create()
826 NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */ in nv20_graph_create()
827 NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */ in nv20_graph_create()
828 NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */ in nv20_graph_create()
831 if (0x00000003 & (1 << (dev_priv->chipset & 0x0f))) in nv20_graph_create()
832 NVOBJ_CLASS(dev, 0x0397, GR); in nv20_graph_create()
834 if (0x00000010 & (1 << (dev_priv->chipset & 0x0f))) in nv20_graph_create()
835 NVOBJ_CLASS(dev, 0x0697, GR); in nv20_graph_create()
837 if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f))) in nv20_graph_create()
838 NVOBJ_CLASS(dev, 0x0497, GR); in nv20_graph_create()
841 return 0; in nv20_graph_create()