Home
last modified time | relevance | path

Searched +full:0 +full:x4000000 (Results 1 – 18 of 18) sorted by relevance

/qemu/tests/qtest/libqos/
H A Dahci.h33 #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
34 #define PCI_MSI_FLAGS_RESERVED (0xFF00)
35 #define PCI_PM_CTRL_RESERVED (0xFC)
37 #define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
38 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
45 #define AHCI_CAP (0)
46 #define AHCI_CAP_NP (0x1F)
47 #define AHCI_CAP_SXS (0x20)
48 #define AHCI_CAP_EMS (0x40)
49 #define AHCI_CAP_CCCS (0x80)
[all …]
/qemu/linux-user/generic/
H A Dtarget_mman.h5 #define TARGET_MAP_SHARED 0x01
6 #define TARGET_MAP_PRIVATE 0x02
7 #define TARGET_MAP_SHARED_VALIDATE 0x03
9 /* 0x0100 - 0x4000 flags are defined in asm-generic/mman.h */
11 #define TARGET_MAP_GROWSDOWN 0x0100
14 #define TARGET_MAP_DENYWRITE 0x0800
17 #define TARGET_MAP_EXECUTABLE 0x1000
20 #define TARGET_MAP_LOCKED 0x2000
23 #define TARGET_MAP_NORESERVE 0x4000
28 #define TARGET_PROT_SEM 0x08
[all …]
/qemu/include/hw/riscv/
H A Dvirt.h39 VIRT_AIA_TYPE_NONE = 0,
98 PCIE_IRQ = 0x20, /* 32 to 35 */
99 IOMMU_SYS_IRQ = 0x24, /* 36-39 */
111 #define VIRT_PLIC_PRIORITY_BASE 0x00
112 #define VIRT_PLIC_PENDING_BASE 0x1000
113 #define VIRT_PLIC_ENABLE_BASE 0x2000
114 #define VIRT_PLIC_ENABLE_STRIDE 0x80
115 #define VIRT_PLIC_CONTEXT_BASE 0x200000
116 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
122 #define FDT_PLIC_ADDR_CELLS 0
[all …]
/qemu/linux-headers/asm-generic/
H A Dmman-common.h10 #define PROT_READ 0x1 /* page can be read */
11 #define PROT_WRITE 0x2 /* page can be written */
12 #define PROT_EXEC 0x4 /* page can be executed */
13 #define PROT_SEM 0x8 /* page may be used for atomic ops */
14 /* 0x10 reserved for arch-specific use */
15 /* 0x20 reserved for arch-specific use */
16 #define PROT_NONE 0x0 /* page can not be accessed */
17 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
18 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
20 /* 0x01 - 0x03 are defined in linux/mman.h */
[all …]
/qemu/util/
H A Dunicode.c18 if (codepoint > 0x10FFFFu) { in is_valid_codepoint()
21 if ((codepoint >= 0xFDD0 && codepoint <= 0xFDEF) in is_valid_codepoint()
22 || (codepoint & 0xFFFE) == 0xFFFE) { in is_valid_codepoint()
25 if (codepoint >= 0xD800 && codepoint <= 0xDFFF) { in is_valid_codepoint()
44 * If @s points to an impossible byte (0xFE or 0xFF) or a continuation
64 static int min_cp[5] = { 0x80, 0x800, 0x10000, 0x200000, 0x4000000 }; in mod_utf8_codepoint()
69 if (n == 0 || *s == 0) { in mod_utf8_codepoint()
77 if (byte < 0x80) { in mod_utf8_codepoint()
79 } else if (byte >= 0xFE) { in mod_utf8_codepoint()
80 cp = -1; /* impossible bytes 0xFE, 0xFF */ in mod_utf8_codepoint()
[all …]
/qemu/include/hw/arm/
H A Dxlnx-versal.h174 #define MM_TOP_RSVD 0xa0000000U
175 #define MM_TOP_RSVD_SIZE 0x4000000
176 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
177 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
178 #define MM_GIC_APU_REDIST_0 0xf9080000U
179 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
181 #define MM_UART0 0xff000000U
182 #define MM_UART0_SIZE 0x10000
183 #define MM_UART1 0xff010000U
184 #define MM_UART1_SIZE 0x10000
[all …]
/qemu/hw/char/
H A Dnrf51_uart.c6 * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
47 return 0; in uart_read()
84 s->watch_tag = 0; in uart_transmit()
87 if (r <= 0) { in uart_transmit()
109 s->watch_tag = 0; in uart_cancel_transmit()
150 if (value == 0) { in uart_write()
151 s->reg[R_UART_RXDRDY] = 0; in uart_write()
203 s->pending_tx_byte = 0; in nrf51_uart_reset()
207 memset(s->reg, 0, sizeof(s->reg)); in nrf51_uart_reset()
209 s->reg[R_UART_PSELRTS] = 0xFFFFFFFF; in nrf51_uart_reset()
[all …]
/qemu/hw/riscv/
H A Dsifive_e.c8 * 0) UART
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
52 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
53 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
54 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
55 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
56 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
57 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
58 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
59 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
[all …]
H A Dmicrochip_pfsoc.c11 * 0) CLINT (Core Level Interruptor)
63 #define RESET_VECTOR 0x20220000
66 #define GEM_REVISION 0x0107010c
87 [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
88 [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
89 [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
90 [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
91 [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
92 [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
93 [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
[all …]
H A Dvirt.c83 [VIRT_DEBUG] = { 0x0, 0x100 },
84 [VIRT_MROM] = { 0x1000, 0xf000 },
85 [VIRT_TEST] = { 0x100000, 0x1000 },
86 [VIRT_RTC] = { 0x101000, 0x1000 },
87 [VIRT_CLINT] = { 0x2000000, 0x10000 },
88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 },
91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[all …]
H A Dsifive_u.c10 * 0) UART
69 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
70 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
71 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
72 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
73 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
74 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
75 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
76 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
77 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
[all …]
/qemu/hw/m68k/
H A Dnext-cube.c38 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
40 #define DPRINTF(fmt, ...) do { } while (0)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
151 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
153 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
158 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
159 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
[all …]
/qemu/hw/display/
H A Dbcm2835_fb.c38 #define DEFAULT_VCRAM_SIZE 0x4000000
39 #define BCM2835_FB_OFFSET 0x00100000
72 r = (rgb888 >> 0) & 0xff; in draw_line_src16()
73 g = (rgb888 >> 8) & 0xff; in draw_line_src16()
74 b = (rgb888 >> 16) & 0xff; in draw_line_src16()
79 r = ((rgb565 >> 11) & 0x1f) << 3; in draw_line_src16()
80 g = ((rgb565 >> 5) & 0x3f) << 2; in draw_line_src16()
81 b = ((rgb565 >> 0) & 0x1f) << 3; in draw_line_src16()
86 r = (rgb888 >> 0) & 0xff; in draw_line_src16()
87 g = (rgb888 >> 8) & 0xff; in draw_line_src16()
[all …]
/qemu/tests/qemu-iotests/
H A D061.out6 wrote 131072/131072 bytes at offset 0
8 magic 0x514649fb
10 backing_file_offset 0x0
11 backing_file_size 0x0
14 crypt_method 0
16 l1_table_offset 0x30000
17 refcount_table_offset 0x10000
19 nb_snapshots 0
20 snapshot_offset 0x0
22 compatible_features [0]
[all …]
/qemu/hw/mips/
H A Dloongson3_virt.c54 #define PM_CNTL_MODE 0x10
65 #define UART_IRQ 0
70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
71 [VIRT_PM] = { 0x10080000, 0x100 },
72 [VIRT_FW_CFG] = { 0x10080100, 0x100 },
73 [VIRT_RTC] = { 0x10081000, 0x1000 },
74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
77 [VIRT_UART] = { 0x1fe001e0, 0x8 },
[all …]
/qemu/target/mips/
H A Dcpu.h44 # define FP_ENDIAN_IDX 0
65 #define FCR0_REV 0
75 } while (0)
79 } while (0)
80 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
81 (((env).fcr31 >> 23) & 0x1))
82 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
83 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
84 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
85 #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
[all …]
/qemu/linux-user/
H A Delfload.c49 #define TARGET_ARCH_HAS_SIGTRAMP_PAGE 0
71 ADDR_NO_RANDOMIZE = 0x0040000, /* disable randomization of VA space */
72 FDPIC_FUNCPTRS = 0x0080000, /* userspace function ptrs point to
74 MMAP_PAGE_ZERO = 0x0100000,
75 ADDR_COMPAT_LAYOUT = 0x0200000,
76 READ_IMPLIES_EXEC = 0x0400000,
77 ADDR_LIMIT_32BIT = 0x0800000,
78 SHORT_INODE = 0x1000000,
79 WHOLE_SECONDS = 0x2000000,
80 STICKY_TIMEOUTS = 0x4000000,
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]