Lines Matching +full:0 +full:x4000000
83 [VIRT_DEBUG] = { 0x0, 0x100 },
84 [VIRT_MROM] = { 0x1000, 0xf000 },
85 [VIRT_TEST] = { 0x100000, 0x1000 },
86 [VIRT_RTC] = { 0x101000, 0x1000 },
87 [VIRT_CLINT] = { 0x2000000, 0x10000 },
88 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
89 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
90 [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 },
91 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
92 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
93 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
94 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
95 [VIRT_UART0] = { 0x10000000, 0x100 },
96 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
97 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
98 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
99 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
100 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
101 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
102 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
103 [VIRT_DRAM] = { 0x80000000, 0x0 },
107 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
131 qdev_prop_set_uint16(dev, "id0", 0x89); in virt_flash_create1()
132 qdev_prop_set_uint16(dev, "id1", 0x18); in virt_flash_create1()
133 qdev_prop_set_uint16(dev, "id2", 0x00); in virt_flash_create1()
134 qdev_prop_set_uint16(dev, "id3", 0x00); in virt_flash_create1()
146 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); in virt_flash_create()
163 0)); in virt_flash_map1()
172 virt_flash_map1(s->flash[0], flashbase, flashsize, in virt_flash_map()
182 uint32_t irq_map_stride = 0; in create_pcie_irq_map()
195 for (dev = 0; dev < PCI_NUM_PINS; dev++) { in create_pcie_irq_map()
196 int devfn = dev * 0x8; in create_pcie_irq_map()
198 for (pin = 0; pin < PCI_NUM_PINS; pin++) { in create_pcie_irq_map()
200 int i = 0; in create_pcie_irq_map()
214 irq_map[i++] = cpu_to_be32(0x4); in create_pcie_irq_map()
229 0x1800, 0, 0, 0x7); in create_pcie_irq_map()
239 bool is_32_bit = riscv_is_32bit(&s->soc[0]); in create_fdt_socket_cpus()
241 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { in create_fdt_socket_cpus()
294 qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); in create_fdt_socket_cpus()
335 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { in create_fdt_socket_clint()
336 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_clint()
350 0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size); in create_fdt_socket_clint()
373 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { in create_fdt_socket_aclint()
374 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_aclint()
376 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_aclint()
378 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_aclint()
392 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); in create_fdt_socket_aclint()
395 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); in create_fdt_socket_aclint()
396 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); in create_fdt_socket_aclint()
415 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, in create_fdt_socket_aclint()
416 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, in create_fdt_socket_aclint()
417 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, in create_fdt_socket_aclint()
418 0x0, RISCV_ACLINT_DEFAULT_MTIME); in create_fdt_socket_aclint()
433 0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size); in create_fdt_socket_aclint()
436 qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); in create_fdt_socket_aclint()
437 qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); in create_fdt_socket_aclint()
454 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt_socket_plic()
469 qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); in create_fdt_socket_plic()
474 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { in create_fdt_socket_plic()
475 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_plic()
485 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { in create_fdt_socket_plic()
486 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_socket_plic()
498 0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size); in create_fdt_socket_plic()
515 uint32_t ret = 0; in imsic_num_bits()
542 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { in create_fdt_one_imsic()
543 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_one_imsic()
547 imsic_max_hart_per_socket = 0; in create_fdt_one_imsic()
548 for (socket = 0; socket < socket_count; socket++) { in create_fdt_one_imsic()
552 imsic_regs[socket * 4 + 0] = 0; in create_fdt_one_imsic()
554 imsic_regs[socket * 4 + 2] = 0; in create_fdt_one_imsic()
570 qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); in create_fdt_one_imsic()
571 qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); in create_fdt_one_imsic()
605 *msi_m_phandle, true, 0); in create_fdt_imsic()
637 for (cpu = 0; cpu < num_harts; cpu++) { in create_fdt_one_aplic()
638 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); in create_fdt_one_aplic()
650 qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); in create_fdt_one_aplic()
660 0x0, aplic_addr, 0x0, aplic_size); in create_fdt_one_aplic()
668 aplic_child_phandle, 0x1, in create_fdt_one_aplic()
677 aplic_child_phandle, 0x1, in create_fdt_one_aplic()
717 aplic_s_phandle, 0, in create_fdt_socket_aplic()
735 RISCVCPU hart = s->soc[0].harts[0]; in create_fdt_pmu()
751 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; in create_fdt_sockets()
759 kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : in create_fdt_sockets()
761 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in create_fdt_sockets()
762 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); in create_fdt_sockets()
768 for (socket = (socket_count - 1); socket >= 0; socket--) { in create_fdt_sockets()
800 create_fdt_socket_aplic(s, 0, in create_fdt_sockets()
802 &intc_phandles[0], xplic_phandles, in create_fdt_sockets()
805 *irq_mmio_phandle = xplic_phandles[0]; in create_fdt_sockets()
806 *irq_virtio_phandle = xplic_phandles[0]; in create_fdt_sockets()
807 *irq_pcie_phandle = xplic_phandles[0]; in create_fdt_sockets()
810 for (socket = (socket_count - 1); socket >= 0; socket--) { in create_fdt_sockets()
826 for (socket = 0; socket < socket_count; socket++) { in create_fdt_sockets()
827 if (socket == 0) { in create_fdt_sockets()
851 for (i = 0; i < VIRTIO_COUNT; i++) { in create_fdt_virtio()
861 0x0, addr, in create_fdt_virtio()
862 0x0, size); in create_fdt_virtio()
870 VIRTIO_IRQ + i, 0x4); in create_fdt_virtio()
889 qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); in create_fdt_pcie()
893 qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); in create_fdt_pcie()
894 qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, in create_fdt_pcie()
896 qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); in create_fdt_pcie()
900 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, in create_fdt_pcie()
901 s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size); in create_fdt_pcie()
903 1, FDT_PCI_RANGE_IOPORT, 2, 0, in create_fdt_pcie()
914 0, iommu_sys_phandle, 0, 0, 0, in create_fdt_pcie()
915 iommu_sys_phandle, 0, 0xffff); in create_fdt_pcie()
939 0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size); in create_fdt_reset()
948 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); in create_fdt_reset()
956 qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); in create_fdt_reset()
972 0x0, s->memmap[VIRT_UART0].base, in create_fdt_uart()
973 0x0, s->memmap[VIRT_UART0].size); in create_fdt_uart()
979 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); in create_fdt_uart()
998 0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size); in create_fdt_rtc()
1004 qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); in create_fdt_rtc()
1035 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_fdt_fw_cfg()
1040 const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; in create_fdt_virtio_iommu()
1056 1, bdf << 8, 1, 0, 1, 0, in create_fdt_virtio_iommu()
1057 1, 0, 1, 0); in create_fdt_virtio_iommu()
1062 0, iommu_phandle, 0, bdf, in create_fdt_virtio_iommu()
1063 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); in create_fdt_virtio_iommu()
1097 iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, in create_fdt_iommu_sys()
1125 bdf << 8, 0, 0, 0, 0); in create_fdt_iommu()
1127 0, iommu_phandle, 0, bdf, in create_fdt_iommu()
1128 bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); in create_fdt_iommu()
1172 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); in create_fdt()
1173 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); in create_fdt()
1176 qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); in create_fdt()
1178 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); in create_fdt()
1179 qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); in create_fdt()
1244 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); in gpex_pcie_init()
1246 ecam_reg, 0, ecam_size); in gpex_pcie_init()
1264 for (i = 0; i < PCI_NUM_PINS; i++) { in gpex_pcie_init()
1312 hwaddr addr = 0; in virt_create_aia()
1323 for (i = 0; i < hart_count; i++) { in virt_create_aia()
1324 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), in virt_create_aia()
1333 for (i = 0; i < hart_count; i++) { in virt_create_aia()
1345 (msimode) ? 0 : base_hartid, in virt_create_aia()
1346 (msimode) ? 0 : hart_count, in virt_create_aia()
1356 (msimode) ? 0 : base_hartid, in virt_create_aia()
1357 (msimode) ? 0 : hart_count, in virt_create_aia()
1384 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { in create_platform_bus()
1391 sysbus_mmio_get_region(sysbus, 0)); in create_platform_bus()
1409 if (riscv_is_32bit(&s->soc[0])) { in virt_build_smbios()
1410 smbios_set_default_processor_family(0x200); in virt_build_smbios()
1412 smbios_set_default_processor_family(0x201); in virt_build_smbios()
1440 const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); in virt_machine_done()
1442 uint64_t kernel_entry = 0; in virt_machine_done()
1473 pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); in virt_machine_done()
1493 riscv_boot_info_init(&boot_info, &s->soc[0]); in virt_machine_done()
1509 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, in virt_machine_done()
1555 for (i = 0; i < socket_count; i++) { in virt_machine_init()
1564 if (base_hartid < 0) { in virt_machine_init()
1570 if (hart_count < 0) { in virt_machine_init()
1635 if (i == 0) { in virt_machine_init()
1657 if (riscv_is_32bit(&s->soc[0])) { in virt_machine_init()
1696 for (i = 0; i < VIRTIO_COUNT; i++) { in virt_machine_init()
1707 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, in virt_machine_init()
1708 serial_hd(0), DEVICE_LITTLE_ENDIAN); in virt_machine_init()
1713 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { in virt_machine_init()
1716 drive_get(IF_PFLASH, 0, i)); in virt_machine_init()
1775 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { in virt_set_aia_guests()
1777 error_append_hint(errp, "Valid values be between 0 and %d.\n", in virt_set_aia_guests()
1967 "Valid value should be between 0 and %d.", in virt_machine_class_init()