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/linux-5.10/include/linux/amba/
Dserial.h20 #define UART01x_DR 0x00 /* Data read or written from the interface. */
21 #define UART01x_RSR 0x04 /* Receive status register (Read). */
22 #define UART01x_ECR 0x04 /* Error clear register (Write). */
23 #define UART010_LCRH 0x08 /* Line control register, high byte. */
24 #define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
25 #define UART010_LCRM 0x0C /* Line control register, middle byte. */
26 #define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
27 #define UART010_LCRL 0x10 /* Line control register, low byte. */
28 #define UART010_CR 0x14 /* Control register. */
29 #define UART01x_FR 0x18 /* Flag register (Read only). */
[all …]
/linux-5.10/sound/soc/codecs/
Dstac9766.c26 #define STAC9766_VENDOR_ID 0x83847666
27 #define STAC9766_VENDOR_ID_MASK 0xffffffff
29 #define AC97_STAC_DA_CONTROL 0x6A
30 #define AC97_STAC_ANALOG_SPECIAL 0x6E
31 #define AC97_STAC_STEREO_MIC 0x78
34 { 0x02, 0x8000 },
35 { 0x04, 0x8000 },
36 { 0x06, 0x8000 },
37 { 0x0a, 0x0000 },
38 { 0x0c, 0x8008 },
[all …]
/linux-5.10/arch/c6x/platforms/
Dcache.c16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
[all …]
/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
144 compatible = "sifive,plic-1.0.0";
145 reg = <0x0 0xc000000 0x0 0x4000000>;
149 &cpu0_intc 0xffffffff
150 &cpu1_intc 0xffffffff &cpu1_intc 9
151 &cpu2_intc 0xffffffff &cpu2_intc 9
152 &cpu3_intc 0xffffffff &cpu3_intc 9
153 &cpu4_intc 0xffffffff &cpu4_intc 9>;
[all …]
/linux-5.10/arch/arc/boot/dts/
Dhsdk.dts22 …bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
63 #clock-cells = <0>;
115 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
120 reg = <0x8a0 0x4>, <0xff0 0x4>;
123 core_clk: core-clk@0 {
125 reg = <0x00 0x10>, <0x14b8 0x4>;
126 #clock-cells = <0>;
[all …]
/linux-5.10/drivers/net/phy/
Dsmsc.c28 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_ 0x0001
32 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_ 0x8000
33 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_ 0x4000
34 #define SPECIAL_CTRL_STS_AMDIX_STATE_ 0x2000
54 u16 intmask = 0; in smsc_phy_config_intr()
65 return rc < 0 ? rc : 0; in smsc_phy_config_intr()
72 return rc < 0 ? rc : 0; in smsc_phy_ack_interrupt()
81 return 0; in smsc_phy_config_init()
85 if (rc < 0) in smsc_phy_config_init()
91 if (rc < 0) in smsc_phy_config_init()
[all …]
/linux-5.10/arch/arm64/include/uapi/asm/
Dkvm.h26 #define KVM_SPSR_EL1 0
66 #define KVM_ARM_TARGET_AEM_V8 0
77 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
78 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
80 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
83 #define KVM_ARM_DEVICE_VGIC_V2 0
86 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
89 #define KVM_VGIC_V2_DIST_SIZE 0x1000
90 #define KVM_VGIC_V2_CPU_SIZE 0x2000
102 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
[all …]
/linux-5.10/tools/arch/arm64/include/uapi/asm/
Dkvm.h26 #define KVM_SPSR_EL1 0
66 #define KVM_ARM_TARGET_AEM_V8 0
77 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
78 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
80 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
83 #define KVM_ARM_DEVICE_VGIC_V2 0
86 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
89 #define KVM_VGIC_V2_DIST_SIZE 0x1000
90 #define KVM_VGIC_V2_CPU_SIZE 0x2000
102 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
[all …]
/linux-5.10/arch/arm/boot/dts/
Dstm32f7-pinctrl.dtsi15 ranges = <0 0x40020000 0x3000>;
17 st,syscfg = <&syscfg 0x8>;
25 reg = <0x0 0x400>;
26 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 reg = <0x400 0x400>;
36 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 reg = <0x800 0x400>;
46 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 reg = <0xc00 0x400>;
56 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
[all …]
Dda850-lego-ev3.dts25 reg = <0xc0000000 0x04000000>;
35 pinctrl-0 = <&button_bias>;
120 pinctrl-0 = <&ehrpwm0b_pins>;
121 pwms = <&ehrpwm0 1 1000000 0>;
143 gpio = <&gpio 101 0>;
184 pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>;
186 #clock-cells = <0>;
188 pwms = <&ecap2 0 30518 0>;
194 reg = <0xffff0000 0x2000>; /* 8k */
202 offset = <0x1ffc>;
[all …]
Dstm32h743-pinctrl.dtsi51 ranges = <0 0x58020000 0x3000>;
53 st,syscfg = <&syscfg 0x8>;
59 reg = <0x0 0x400>;
69 reg = <0x400 0x400>;
79 reg = <0x800 0x400>;
89 reg = <0xc00 0x400>;
99 reg = <0x1000 0x400>;
109 reg = <0x1400 0x400>;
119 reg = <0x1800 0x400>;
129 reg = <0x1c00 0x400>;
[all …]
/linux-5.10/drivers/rtc/
Drtc-ds1553.c20 #define RTC_REG_SIZE 0x2000
21 #define RTC_OFFSET 0x1ff0
23 #define RTC_FLAGS (RTC_OFFSET + 0)
40 #define RTC_CENTURY_MASK 0x3f
41 #define RTC_SECONDS_MASK 0x7f
42 #define RTC_DAY_MASK 0x07
45 #define RTC_WRITE 0x80
46 #define RTC_READ 0x40
49 #define RTC_STOP 0x80
52 #define RTC_FLAGS_AF 0x40
[all …]
/linux-5.10/arch/mips/include/asm/ip32/
Dmace.h18 #define MACE_BASE 0x1f000000 /* physical */
43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST 0
45 #define MACEPCI_ERROR_DEVSEL_MED 0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
48 #define MACEPCI_ERROR_66MHZ BIT(0)
51 #define MACEPCI_CONTROL_INT_MASK 0xff
61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
71 unsigned int _pad[0xcf8/4 - 4];
79 #define MACEPCI_LOW_MEMORY 0x1a000000
[all …]
/linux-5.10/drivers/rapidio/switches/
Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/linux-5.10/drivers/s390/crypto/
Dzcrypt_ccamisc.h17 #define TOKTYPE_NON_CCA 0x00 /* Non-CCA key token */
18 #define TOKTYPE_CCA_INTERNAL 0x01 /* CCA internal sym key token */
19 #define TOKTYPE_CCA_INTERNAL_PKA 0x1f /* CCA internal asym key token */
22 #define TOKVER_PROTECTED_KEY 0x01 /* Protected key token */
23 #define TOKVER_CLEAR_KEY 0x02 /* Clear key token */
26 #define TOKVER_CCA_AES 0x04 /* CCA AES key token */
27 #define TOKVER_CCA_VLSC 0x05 /* var length sym cipher key token */
41 /* inside view of a CCA secure key token (only type 0x01 version 0x04) */
43 u8 type; /* 0x01 for internal key token */
45 u8 version; /* should be 0x04 */
[all …]
/linux-5.10/drivers/net/ethernet/rocker/
Drocker_hw.h15 ROCKER_OK = 0,
28 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
30 #define ROCKER_PCI_BAR0_SIZE 0x2000
49 #define ROCKER_BOGUS_REG0 0x0000
50 #define ROCKER_BOGUS_REG1 0x0004
51 #define ROCKER_BOGUS_REG2 0x0008
52 #define ROCKER_BOGUS_REG3 0x000c
55 #define ROCKER_TEST_REG 0x0010
56 #define ROCKER_TEST_REG64 0x0018 /* 8-byte */
57 #define ROCKER_TEST_IRQ 0x0020
[all …]
/linux-5.10/arch/alpha/math-emu/
Dmath.c15 #define OPC_PAL 0x00
16 #define OPC_INTA 0x10
17 #define OPC_INTL 0x11
18 #define OPC_INTS 0x12
19 #define OPC_INTM 0x13
20 #define OPC_FLTC 0x14
21 #define OPC_FLTV 0x15
22 #define OPC_FLTI 0x16
23 #define OPC_FLTL 0x17
24 #define OPC_MISC 0x18
[all …]
/linux-5.10/Documentation/devicetree/bindings/dma/
Dti-edma.txt25 <&tptc_phandle TC_priority_number>. The highest priority is 0.
86 reg = <0x49000000 0x10000>;
93 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
100 dma-channel-mask = <0xffffffff /* Channel 0-31 */
101 0xffffe007>; /* Channel 32-63 */
107 reg = <0x49800000 0x100000>;
115 reg = <0x49900000 0x100000>;
123 reg = <0x49a00000 0x100000>;
131 reg = <0x53100000 0x200>;
134 dmas = <&edma 36 0>;
[all …]
/linux-5.10/arch/m68k/kernel/
Dprocess.c48 __asm__("stop #0x2200" : : : "cc"); in arch_cpu_idle()
50 __asm__("stop #0x2000" : : : "cc"); in arch_cpu_idle()
98 unsigned long zero = 0; in flush_thread()
99 asm volatile("frestore %0": :"m" (zero)); in flush_thread()
162 memset(frame, 0, sizeof(struct fork_frame)); in copy_thread()
167 p->thread.usp = 0; in copy_thread()
168 return 0; in copy_thread()
172 frame->regs.d0 = 0; in copy_thread()
182 asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory"); in copy_thread()
184 if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) { in copy_thread()
[all …]
/linux-5.10/drivers/s390/scsi/
Dzfcp_def.h47 #define FSF_QTCB_UNSOLICITED_STATUS 0x6305
55 #define ZFCP_COMMON_FLAGS 0xfff00000
58 #define ZFCP_STATUS_COMMON_RUNNING 0x40000000
59 #define ZFCP_STATUS_COMMON_ERP_FAILED 0x20000000
60 #define ZFCP_STATUS_COMMON_UNBLOCKED 0x10000000
61 #define ZFCP_STATUS_COMMON_OPEN 0x04000000
62 #define ZFCP_STATUS_COMMON_ERP_INUSE 0x01000000
63 #define ZFCP_STATUS_COMMON_ACCESS_DENIED 0x00800000
64 #define ZFCP_STATUS_COMMON_ACCESS_BOXED 0x00400000
65 #define ZFCP_STATUS_COMMON_NOESC 0x00200000
[all …]
/linux-5.10/drivers/hwmon/
Dtmp108.c23 #define TMP108_REG_TEMP 0x00
24 #define TMP108_REG_CONF 0x01
25 #define TMP108_REG_TLOW 0x02
26 #define TMP108_REG_THIGH 0x03
34 #define TMP108_CONF_M0 0x0100 /* Sensor mode. */
35 #define TMP108_CONF_M1 0x0200
36 #define TMP108_CONF_TM 0x0400 /* Thermostat mode. */
37 #define TMP108_CONF_FL 0x0800 /* Watchdog flag - TLOW */
38 #define TMP108_CONF_FH 0x1000 /* Watchdog flag - THIGH */
39 #define TMP108_CONF_CR0 0x2000 /* Conversion rate. */
[all …]
/linux-5.10/drivers/irqchip/
Dirq-sifive-plic.c28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
40 #define PRIORITY_BASE 0
47 #define ENABLE_BASE 0x2000
48 #define ENABLE_PER_HART 0x80
55 #define CONTEXT_BASE 0x200000
56 #define CONTEXT_PER_HART 0x1000
57 #define CONTEXT_THRESHOLD 0x00
58 #define CONTEXT_CLAIM 0x04
60 #define PLIC_DISABLE_THRESHOLD 0x7
[all …]
/linux-5.10/drivers/scsi/arm/
Darxescsi.c12 * 30-08-1997 RMK 0.0.0 Created, READONLY version as cumana_2.c
17 * 01-01-2000 SH 0.1.0 Added *real* pseudo dma writing
48 #define DMADATA_OFFSET (0x200)
50 #define DMASTAT_OFFSET (0x600)
51 #define DMASTAT_DRQ (1 << 0)
53 #define CSTATUS_IRQ (1 << 0)
64 * Returns : 0 if we should not set CMD_WITHDMA for transfer info command
80 " mov r3, %0\n" in arxescsi_pseudo_dma_write()
117 unsigned int length, error = 0; in arxescsi_dma_pseudo()
127 if (readb(base + 0x80) & STAT_INT) { in arxescsi_dma_pseudo()
[all …]
/linux-5.10/drivers/gpio/
Dgpio-lpc18xx.c23 #define LPC18XX_REG_DIR(n) (0x2000 + n * sizeof(u32))
29 #define LPC18XX_GPIO_PIN_IC_ISEL 0x00
30 #define LPC18XX_GPIO_PIN_IC_IENR 0x04
31 #define LPC18XX_GPIO_PIN_IC_SIENR 0x08
32 #define LPC18XX_GPIO_PIN_IC_CIENR 0x0c
33 #define LPC18XX_GPIO_PIN_IC_IENF 0x10
34 #define LPC18XX_GPIO_PIN_IC_SIENF 0x14
35 #define LPC18XX_GPIO_PIN_IC_CIENF 0x18
36 #define LPC18XX_GPIO_PIN_IC_RISE 0x1c
37 #define LPC18XX_GPIO_PIN_IC_FALL 0x20
[all …]

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