drivers/irqchip/irq-sifive-plic.c

28  * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29  * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
40 #define PRIORITY_BASE			0
47 #define ENABLE_BASE			0x2000
48 #define     ENABLE_PER_HART		0x80
55 #define CONTEXT_BASE			0x200000
56 #define     CONTEXT_PER_HART		0x1000
57 #define     CONTEXT_THRESHOLD		0x00
58 #define     CONTEXT_CLAIM		0x04
60 #define	PLIC_DISABLE_THRESHOLD		0x7
61 #define	PLIC_ENABLE_THRESHOLD		0
132 	plic_irq_toggle(&priv->lmask, d, 0);  in plic_irq_mask()
153 	plic_irq_toggle(&priv->lmask, d, 0);  in plic_set_affinity()
188 	return 0;  in plic_irqdomain_map()
203 	for (i = 0; i < nr_irqs; i++) {  in plic_irq_domain_alloc()
209 	return 0;  in plic_irq_domain_alloc()
238 		if (unlikely(irq <= 0))  in plic_handle_irq()
259 	return 0;  in plic_dying_cpu()
273 	return 0;  in plic_starting_cpu()
279 	int error = 0, nr_contexts, nr_handlers = 0, i;  in plic_init()
288 	priv->regs = of_iomap(node, 0);  in plic_init()
309 	for (i = 0; i < nr_contexts; i++) {  in plic_init()
323 		if (parent.args[0] != RV_IRQ_EXT)  in plic_init()
327 		if (hartid < 0) {  in plic_init()
333 		if (cpu < 0) {  in plic_init()
368 			plic_toggle(handler, hwirq, 0);  in plic_init()
386 	return 0;  in plic_init()
395 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);