Lines Matching +full:0 +full:x2000
26 #define KVM_SPSR_EL1 0
66 #define KVM_ARM_TARGET_AEM_V8 0
77 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
78 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
80 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
83 #define KVM_ARM_DEVICE_VGIC_V2 0
86 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
89 #define KVM_VGIC_V2_DIST_SIZE 0x1000
90 #define KVM_VGIC_V2_CPU_SIZE 0x2000
102 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
170 #define KVM_PMU_EVENT_ALLOW 0
191 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
195 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
199 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
200 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
202 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
203 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
204 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
207 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
208 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
210 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
212 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
214 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
216 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
217 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
236 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
248 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
252 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
254 KVM_REG_ARM_FW | ((r) & 0xffff))
255 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
257 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
270 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
277 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
280 #define KVM_REG_ARM64_SVE_ZREG_BASE 0
281 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400
282 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600
318 KVM_REG_SIZE_U512 | 0xffff)
323 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0
327 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
330 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
331 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
332 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
333 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
342 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
343 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
344 #define VGIC_LEVEL_INFO_LINE_LEVEL 0
346 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
353 #define KVM_ARM_VCPU_PMU_V3_CTRL 0
354 #define KVM_ARM_VCPU_PMU_V3_IRQ 0
358 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
361 #define KVM_ARM_VCPU_PVTIME_IPA 0
365 #define KVM_ARM_IRQ_VCPU2_MASK 0xf
367 #define KVM_ARM_IRQ_TYPE_MASK 0xf
369 #define KVM_ARM_IRQ_VCPU_MASK 0xff
370 #define KVM_ARM_IRQ_NUM_SHIFT 0
371 #define KVM_ARM_IRQ_NUM_MASK 0xffff
374 #define KVM_ARM_IRQ_TYPE_CPU 0
379 #define KVM_ARM_IRQ_CPU_IRQ 0
395 #define KVM_PSCI_FN_BASE 0x95c1ba5e
398 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)