Lines Matching +full:0 +full:x2000
20 #define UART01x_DR 0x00 /* Data read or written from the interface. */
21 #define UART01x_RSR 0x04 /* Receive status register (Read). */
22 #define UART01x_ECR 0x04 /* Error clear register (Write). */
23 #define UART010_LCRH 0x08 /* Line control register, high byte. */
24 #define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
25 #define UART010_LCRM 0x0C /* Line control register, middle byte. */
26 #define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
27 #define UART010_LCRL 0x10 /* Line control register, low byte. */
28 #define UART010_CR 0x14 /* Control register. */
29 #define UART01x_FR 0x18 /* Flag register (Read only). */
30 #define UART010_IIR 0x1C /* Interrupt identification register (Read). */
31 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */
32 #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
33 #define UART01x_ILPR 0x20 /* IrDA low power counter register. */
34 #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
35 #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
36 #define UART011_LCRH 0x2c /* Line control register. */
37 #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
38 #define UART011_CR 0x30 /* Control register. */
39 #define UART011_IFLS 0x34 /* Interrupt fifo level select. */
40 #define UART011_IMSC 0x38 /* Interrupt mask. */
41 #define UART011_RIS 0x3c /* Raw interrupt status. */
42 #define UART011_MIS 0x40 /* Masked interrupt status. */
43 #define UART011_ICR 0x44 /* Interrupt clear register. */
44 #define UART011_DMACR 0x48 /* DMA control register. */
45 #define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
46 #define ST_UART011_XON1 0x54 /* XON1 register. */
47 #define ST_UART011_XON2 0x58 /* XON2 register. */
48 #define ST_UART011_XOFF1 0x5C /* XON1 register. */
49 #define ST_UART011_XOFF2 0x60 /* XON2 register. */
50 #define ST_UART011_ITCR 0x80 /* Integration test control register. */
51 #define ST_UART011_ITIP 0x84 /* Integration test input register. */
52 #define ST_UART011_ABCR 0x100 /* Autobaud control register. */
53 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
60 #define ZX_UART011_DR 0x04
61 #define ZX_UART011_FR 0x14
62 #define ZX_UART011_IBRD 0x24
63 #define ZX_UART011_FBRD 0x28
64 #define ZX_UART011_LCRH 0x30
65 #define ZX_UART011_CR 0x34
66 #define ZX_UART011_IFLS 0x38
67 #define ZX_UART011_IMSC 0x40
68 #define ZX_UART011_RIS 0x44
69 #define ZX_UART011_MIS 0x48
70 #define ZX_UART011_ICR 0x4c
71 #define ZX_UART011_DMACR 0x50
78 #define UART01x_RSR_OE 0x08
79 #define UART01x_RSR_BE 0x04
80 #define UART01x_RSR_PE 0x02
81 #define UART01x_RSR_FE 0x01
83 #define UART011_FR_RI 0x100
84 #define UART011_FR_TXFE 0x080
85 #define UART011_FR_RXFF 0x040
86 #define UART01x_FR_TXFF 0x020
87 #define UART01x_FR_RXFE 0x010
88 #define UART01x_FR_BUSY 0x008
89 #define UART01x_FR_DCD 0x004
90 #define UART01x_FR_DSR 0x002
91 #define UART01x_FR_CTS 0x001
98 #define ZX_UART01x_FR_BUSY 0x100
99 #define ZX_UART01x_FR_DSR 0x008
100 #define ZX_UART01x_FR_CTS 0x002
101 #define ZX_UART011_FR_RI 0x001
103 #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
104 #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
105 #define UART011_CR_OUT2 0x2000 /* OUT2 */
106 #define UART011_CR_OUT1 0x1000 /* OUT1 */
107 #define UART011_CR_RTS 0x0800 /* RTS */
108 #define UART011_CR_DTR 0x0400 /* DTR */
109 #define UART011_CR_RXE 0x0200 /* receive enable */
110 #define UART011_CR_TXE 0x0100 /* transmit enable */
111 #define UART011_CR_LBE 0x0080 /* loopback enable */
112 #define UART010_CR_RTIE 0x0040
113 #define UART010_CR_TIE 0x0020
114 #define UART010_CR_RIE 0x0010
115 #define UART010_CR_MSIE 0x0008
116 #define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */
117 #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
118 #define UART01x_CR_SIREN 0x0002 /* SIR enable */
119 #define UART01x_CR_UARTEN 0x0001 /* UART enable */
121 #define UART011_LCRH_SPS 0x80
122 #define UART01x_LCRH_WLEN_8 0x60
123 #define UART01x_LCRH_WLEN_7 0x40
124 #define UART01x_LCRH_WLEN_6 0x20
125 #define UART01x_LCRH_WLEN_5 0x00
126 #define UART01x_LCRH_FEN 0x10
127 #define UART01x_LCRH_STP2 0x08
128 #define UART01x_LCRH_EPS 0x04
129 #define UART01x_LCRH_PEN 0x02
130 #define UART01x_LCRH_BRK 0x01
132 #define ST_UART011_DMAWM_RX_1 (0 << 3)
139 #define ST_UART011_DMAWM_TX_1 0
147 #define UART010_IIR_RTIS 0x08
148 #define UART010_IIR_TIS 0x04
149 #define UART010_IIR_RIS 0x02
150 #define UART010_IIR_MIS 0x01
152 #define UART011_IFLS_RX1_8 (0 << 3)
157 #define UART011_IFLS_TX1_8 (0 << 0)
158 #define UART011_IFLS_TX2_8 (1 << 0)
159 #define UART011_IFLS_TX4_8 (2 << 0)
160 #define UART011_IFLS_TX6_8 (3 << 0)
161 #define UART011_IFLS_TX7_8 (4 << 0)
164 #define UART011_IFLS_TX_HALF (5 << 0)
176 #define UART011_RIMIM (1 << 0) /* RI interrupt mask */
188 #define UART011_RIMIS (1 << 0) /* RI interrupt status */
200 #define UART011_RIMIC (1 << 0) /* RI interrupt clear */
204 #define UART011_RXDMAE (1 << 0) /* enable receive dma */