15 #define	OPC_PAL		0x00
16 #define OPC_INTA	0x10
17 #define OPC_INTL	0x11
18 #define OPC_INTS	0x12
19 #define OPC_INTM	0x13
20 #define OPC_FLTC	0x14
21 #define OPC_FLTV	0x15
22 #define OPC_FLTI	0x16
23 #define OPC_FLTL	0x17
24 #define OPC_MISC	0x18
25 #define	OPC_JSR		0x1a
27 #define FOP_SRC_S	0
31 #define FOP_FNC_ADDx	0
32 #define FOP_FNC_CVTQL	0
45 #define MISC_TRAPB	0x0000
46 #define MISC_EXCB	0x0400
74 	return 0;  in init_module()
94  * the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
113 	fc     = (insn >>  0) & 0x1f;	/* destination register */  in alpha_fp_emul()
114 	fb     = (insn >> 16) & 0x1f;  in alpha_fp_emul()
115 	fa     = (insn >> 21) & 0x1f;  in alpha_fp_emul()
116 	func   = (insn >>  5) & 0xf;  in alpha_fp_emul()
117 	src    = (insn >>  9) & 0x3;  in alpha_fp_emul()
118 	mode   = (insn >> 11) & 0x3;  in alpha_fp_emul()
177 			vc = 0x4000000000000000UL;  in alpha_fp_emul()
187 			case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;  in alpha_fp_emul()
188 			case FOP_FNC_CMPxEQ: if (res) vc = 0; break;  in alpha_fp_emul()
189 			case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;  in alpha_fp_emul()
190 			case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;  in alpha_fp_emul()
223 			if (insn & 0x2000) {  in alpha_fp_emul()
240 				vc = 0;  in alpha_fp_emul()
256 			vc = ((vb & 0xc0000000) << 32 |	/* sign and msb */  in alpha_fp_emul()
257 			      (vb & 0x3fffffff) << 29);	/* rest of the int */  in alpha_fp_emul()
276 		vc = 0;  in alpha_fp_emul()
283 		vc = 0;  in alpha_fp_emul()
314 		si_code = 0;  in alpha_fp_emul()
331 	return 0;  in alpha_fp_emul()
343 	unsigned long insn, opcode, rc, si_code = 0;  in alpha_fp_emul_imprecise()
359 		rc = insn & 0x1f;  in alpha_fp_emul_imprecise()
364 		      case 0x30 ... 0x3f:	/* branches */  in alpha_fp_emul_imprecise()
368 			switch (insn & 0xffff) {  in alpha_fp_emul_imprecise()