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Searched +full:0 +full:x10000000 (Results 1 – 25 of 120) sorted by relevance

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/qemu/include/hw/arm/
H A Dfsl-imx31.h60 #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
61 #define FSL_IMX31_SECURE_ROM_SIZE 0x4000
62 #define FSL_IMX31_ROM_ADDR 0x00404000
63 #define FSL_IMX31_ROM_SIZE 0x4000
64 #define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
65 #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
66 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000
67 #define FSL_IMX31_IRAM_SIZE 0x4000
68 #define FSL_IMX31_I2C1_ADDR 0x43F80000
69 #define FSL_IMX31_I2C1_SIZE 0x4000
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H A Dnrf51.h6 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
18 #define NRF51_FLASH_BASE 0x00000000
19 #define NRF51_FICR_BASE 0x10000000
20 #define NRF51_FICR_SIZE 0x00000100
21 #define NRF51_UICR_BASE 0x10001000
22 #define NRF51_SRAM_BASE 0x20000000
24 #define NRF51_IOMEM_BASE 0x40000000
25 #define NRF51_IOMEM_SIZE 0x20000000
27 #define NRF51_PERIPHERAL_SIZE 0x00001000
28 #define NRF51_UART_BASE 0x40002000
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H A Dstm32f405_soc.h47 #define FLASH_BASE_ADDRESS 0x08000000
49 #define SRAM_BASE_ADDRESS 0x20000000
51 #define CCM_BASE_ADDRESS 0x10000000
H A Dfsl-imx25.h74 * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
75 * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved
76 * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)
77 * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
78 * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved
79 * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved
80 * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved
81 * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved
82 * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
83 * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
[all …]
/qemu/hw/sparc/
H A Dsun4m.c75 #define KERNEL_LOAD_ADDR 0x00004000
76 #define CMDLINE_ADDR 0x007ff000
77 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_VADDR 0xffd00000
81 #define CFG_ADDR 0xd00000510ULL
82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
132 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { in DECLARE_CLASS_CHECKERS()
143 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); in fw_cfg_boot_set()
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/qemu/hw/fsi/
H A Dfsi-master.c19 #define FSI_MENP0 TO_REG(0x010)
20 #define FSI_MENP32 TO_REG(0x014)
21 #define FSI_MSENP0 TO_REG(0x018)
22 #define FSI_MLEVP0 TO_REG(0x018)
23 #define FSI_MSENP32 TO_REG(0x01c)
24 #define FSI_MLEVP32 TO_REG(0x01c)
25 #define FSI_MCENP0 TO_REG(0x020)
26 #define FSI_MREFP0 TO_REG(0x020)
27 #define FSI_MCENP32 TO_REG(0x024)
28 #define FSI_MREFP32 TO_REG(0x024)
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/qemu/hw/arm/
H A Dversatilepb.c32 #define VERSATILE_FLASH_ADDR 0x34000000
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
103 case 0: /* STATUS */ in vpb_sic_read()
115 "vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
116 return 0; in vpb_sic_read()
141 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
150 "vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
170 for (i = 0; i < 32; i++) { in vpb_sic_init()
175 "vpb-sic", 0x1000); in vpb_sic_init()
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H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
56 0x33b,
57 0x33b,
58 0x769,
59 0x76d
70 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
72 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
73 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
95 int is_mpcore = 0; in realview_init()
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H A Dstrongarm.h7 #define SA_CS0 0x00000000
8 #define SA_CS1 0x08000000
9 #define SA_CS2 0x10000000
10 #define SA_CS3 0x18000000
11 #define SA_PCMCIA_CS0 0x20000000
12 #define SA_PCMCIA_CS1 0x30000000
13 #define SA_CS4 0x40000000
14 #define SA_CS5 0x48000000
16 #define SA_SDCS0 0xc0000000
17 #define SA_SDCS1 0xc8000000
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H A Domap_sx1.c46 * - SDRAM 32 MB at 0x10000000
47 * - Boot flash 16 MB at 0x00000000
48 * - Application flash 8 MB at 0x04000000
59 * - SDRAM 32 MB at 0x10000000
60 * - Boot flash 32 MB at 0x00000000
96 .board_id = 0x265,
106 static uint32_t cs0val = 0x00213090; in sx1_init()
107 static uint32_t cs1val = 0x00215070; in sx1_init()
108 static uint32_t cs2val = 0x00001139; in sx1_init()
109 static uint32_t cs3val = 0x00001139; in sx1_init()
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/qemu/tests/qtest/libqos/
H A Dmalloc-spapr.c16 #define SPAPR_MIN_SIZE 0x10000000
H A Darm-sabrelite-machine.c27 #define SABRELITE_RAM_START 0x10000000
28 #define SABRELITE_RAM_END 0x30000000
70 alloc_init(&machine->alloc, 0, in qos_create_machine_arm_sabrelite()
77 qos_init_sdhci_mm(&machine->sdhci, qts, 0x02190000, &(QSDHCIProperties) { in qos_create_machine_arm_sabrelite()
79 .baseclock = 0, in qos_create_machine_arm_sabrelite()
81 .capab.reg = 0x057834b4, in qos_create_machine_arm_sabrelite()
/qemu/linux-user/generic/
H A Dsignal.h11 #define TARGET_SA_NOCLDSTOP 0x00000001
12 #define TARGET_SA_NOCLDWAIT 0x00000002 /* not supported yet */
13 #define TARGET_SA_SIGINFO 0x00000004
14 #define TARGET_SA_ONSTACK 0x08000000
15 #define TARGET_SA_RESTART 0x10000000
16 #define TARGET_SA_NODEFER 0x40000000
17 #define TARGET_SA_RESETHAND 0x80000000
53 #define TARGET_SIG_BLOCK 0 /* for blocking signals */
/qemu/include/hw/loongarch/
H A Dvirt.h18 #define VIRT_FWCFG_BASE 0x1e020000UL
19 #define VIRT_BIOS_BASE 0x1c000000UL
24 #define VIRT_FLASH1_BASE 0x1d000000UL
27 #define VIRT_LOWMEM_BASE 0
28 #define VIRT_LOWMEM_SIZE 0x10000000
29 #define VIRT_HIGHMEM_BASE 0x80000000
30 #define VIRT_GED_EVT_ADDR 0x100e0000
37 #define FDT_BASE 0x100000
/qemu/hw/net/
H A De1000x_regs.h36 #define E1000_DEV_ID_82542 0x1000
37 #define E1000_DEV_ID_82543GC_FIBER 0x1001
38 #define E1000_DEV_ID_82543GC_COPPER 0x1004
39 #define E1000_DEV_ID_82544EI_COPPER 0x1008
40 #define E1000_DEV_ID_82544EI_FIBER 0x1009
41 #define E1000_DEV_ID_82544GC_COPPER 0x100C
42 #define E1000_DEV_ID_82544GC_LOM 0x100D
43 #define E1000_DEV_ID_82540EM 0x100E
44 #define E1000_DEV_ID_82540EM_LOM 0x1015
45 #define E1000_DEV_ID_82540EP_LOM 0x1016
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/qemu/tests/qtest/
H A Dendianness-test.c30 { "mips", "malta", 0x10000000, .bswap = true },
31 { "mipsel", "malta", 0x10000000 },
32 { "mips64", "magnum", 0x90000000, .bswap = true },
33 { "mips64", "pica61", 0x90000000, .bswap = true },
34 { "mips64", "malta", 0x10000000, .bswap = true },
35 { "mips64el", "fuloong2e", 0x1fd00000 },
36 { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
37 { "ppc", "40p", 0x80000000, .bswap = true },
38 { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
39 { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
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/qemu/include/hw/xen/interface/
H A Darch-arm.h153 #define XEN_HYPERCALL_TAG 0XEA1
182 _sxghr_tmp->q = 0; \
184 } while ( 0 )
277 #define _VGCF_online 0
293 #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0
297 #define XEN_DOMCTL_CONFIG_TEE_NONE 0
316 * = 0 => property not present
317 * > 0 => Value of the property
345 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */
350 #define PSR_MODE_USR 0x10
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/qemu/hw/ssi/
H A Daspeed_smc.c41 #define R_CONF (0x00 / 4)
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
58 #define R_CE_CTRL (0x04 / 4)
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
66 #define R_INTR_CTRL (0x08 / 4)
75 #define R_CE_CMD_CTRL (0x0C / 4)
77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
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/qemu/hw/m68k/
H A Dan5206.c19 #define KERNEL_LOAD_ADDR 0x10000
20 #define AN5206_MBAR_ADDR 0x10000000
21 #define AN5206_RAMBAR_ADDR 0x20000000
34 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); in mcf5206_init()
53 env->vbr = 0; in an5206_init()
59 memory_region_add_subregion(address_space_mem, 0, machine->ram); in an5206_init()
77 NULL, NULL, NULL, ELFDATA2MSB, EM_68K, 0, 0); in an5206_init()
79 if (kernel_size < 0) { in an5206_init()
83 if (kernel_size < 0) { in an5206_init()
88 if (kernel_size < 0) { in an5206_init()
/qemu/hw/display/
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
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/qemu/include/hw/i386/
H A Dmicrovm.h33 * 0 | pit |
37 * 4 | serial 0 | serial
47 * 14 | ide 0 | pcie
53 #define VIRTIO_MMIO_BASE 0xfeb00000
56 #define GED_MMIO_BASE 0xfea00000
57 #define GED_MMIO_BASE_MEMHP (GED_MMIO_BASE + 0x100)
58 #define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
61 #define MICROVM_XHCI_BASE 0xfe900000
64 #define PCIE_MMIO_BASE 0xc0000000
65 #define PCIE_MMIO_SIZE 0x20000000
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/qemu/linux-user/mips/
H A Dtarget_signal.h60 #define TARGET_SA_NOCLDSTOP 0x00000001
61 #define TARGET_SA_NOCLDWAIT 0x00010000
62 #define TARGET_SA_SIGINFO 0x00000008
63 #define TARGET_SA_ONSTACK 0x08000000
64 #define TARGET_SA_NODEFER 0x40000000
65 #define TARGET_SA_RESTART 0x10000000
66 #define TARGET_SA_RESETHAND 0x80000000
67 #define TARGET_SA_RESTORER 0x04000000 /* Only for O32 */
/qemu/linux-user/mips64/
H A Dtarget_signal.h59 #define TARGET_SA_NOCLDSTOP 0x00000001
60 #define TARGET_SA_NOCLDWAIT 0x00010000
61 #define TARGET_SA_SIGINFO 0x00000008
62 #define TARGET_SA_ONSTACK 0x08000000
63 #define TARGET_SA_NODEFER 0x40000000
64 #define TARGET_SA_RESTART 0x10000000
65 #define TARGET_SA_RESETHAND 0x80000000
/qemu/target/ppc/
H A Dmmu-hash32.h16 #define SR32_T 0x80000000
17 #define SR32_KS 0x40000000
18 #define SR32_KP 0x20000000
19 #define SR32_NX 0x10000000
20 #define SR32_VSID 0x00ffffff
26 #define BATU32_BEPIU 0xf0000000
27 #define BATU32_BEPIL 0x0ffe0000
28 #define BATU32_BEPI 0xfffe0000
29 #define BATU32_BL 0x00001ffc
30 #define BATU32_VS 0x00000002
[all …]
/qemu/target/microblaze/
H A Dcpu.h44 #define MB_CPU_IRQ 0
49 #define SR_PC 0
54 #define SR_BTR 0xb
55 #define SR_EDR 0xd
58 #define MSR_BE (1<<0) /* 0x001 */
59 #define MSR_IE (1<<1) /* 0x002 */
60 #define MSR_C (1<<2) /* 0x004 */
61 #define MSR_BIP (1<<3) /* 0x008 */
62 #define MSR_FSL (1<<4) /* 0x010 */
63 #define MSR_ICE (1<<5) /* 0x020 */
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