Lines Matching +full:0 +full:x10000000
41 #define R_CONF (0x00 / 4)
52 #define CONF_FLASH_TYPE0 0
53 #define CONF_FLASH_TYPE_NOR 0x0
54 #define CONF_FLASH_TYPE_NAND 0x1
55 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
58 #define R_CE_CTRL (0x04 / 4)
63 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
66 #define R_INTR_CTRL (0x08 / 4)
75 #define R_CE_CMD_CTRL (0x0C / 4)
77 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
85 #define R_CTRL0 (0x10 / 4)
92 #define CTRL_CMD_MASK 0xff
96 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
101 #define CTRL_CMD_MODE_MASK 0x3
102 #define CTRL_READMODE 0x0
103 #define CTRL_FREADMODE 0x1
104 #define CTRL_WRITEMODE 0x2
105 #define CTRL_USERMODE 0x3
106 #define R_CTRL1 (0x14 / 4)
107 #define R_CTRL2 (0x18 / 4)
108 #define R_CTRL3 (0x1C / 4)
109 #define R_CTRL4 (0x20 / 4)
112 #define R_SEG_ADDR0 (0x30 / 4)
114 #define SEG_END_MASK 0xff
116 #define SEG_START_MASK 0xff
117 #define R_SEG_ADDR1 (0x34 / 4)
118 #define R_SEG_ADDR2 (0x38 / 4)
119 #define R_SEG_ADDR3 (0x3C / 4)
120 #define R_SEG_ADDR4 (0x40 / 4)
123 #define R_MISC_CTRL1 (0x50 / 4)
126 #define R_DUMMY_DATA (0x54 / 4)
129 #define R_FMC_WDT2_CTRL (0x64 / 4)
133 #define FMC_WDT2_CTRL_EN BIT(0)
136 #define R_DMA_DRAM_ADDR_HIGH (0x7c / 4)
139 #define R_DMA_CTRL (0x80 / 4)
142 #define DMA_CTRL_DELAY_MASK 0xf
144 #define DMA_CTRL_FREQ_MASK 0xf
149 #define DMA_CTRL_ENABLE (1 << 0)
152 #define R_DMA_FLASH_ADDR (0x84 / 4)
155 #define R_DMA_DRAM_ADDR (0x88 / 4)
158 #define R_DMA_LEN (0x8C / 4)
161 #define R_DMA_CHECKSUM (0x90 / 4)
164 #define R_TIMINGS (0x94 / 4)
167 #define R_SPI_CONF (0x00 / 4)
168 #define SPI_CONF_ENABLE_W0 0
169 #define R_SPI_CTRL0 (0x4 / 4)
170 #define R_SPI_MISC_CTRL (0x10 / 4)
171 #define R_SPI_TIMINGS (0x14 / 4)
173 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
174 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
178 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
179 * 0x80000000 - 0xBFFFFFFF (AST2500)
182 * range is 0x20000000 - 0x2FFFFFFF.
185 * 0: 4 bytes
186 * 0x1FFFFFC: 32M bytes
189 * 0: 1 byte
190 * 0x1FFFFFF: 32M bytes
193 #define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf)
195 #define DMA_LENGTH(val) ((val) & 0x01FFFFFF)
198 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
200 #define SNOOP_OFF 0xFF
201 #define SNOOP_START 0x0
211 #define ASPEED_SMC_FEATURE_DMA 0x1
212 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
213 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
214 #define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08
242 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_flash_overlap()
251 aspeed_smc_error("new segment CS%d [ 0x%" in aspeed_smc_flash_overlap()
252 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " in aspeed_smc_flash_overlap()
253 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_overlap()
295 if (cs == 0 && seg.addr != asc->flash_window_base) { in aspeed_smc_flash_set_segment()
296 aspeed_smc_error("Tried to change CS0 start address to 0x%" in aspeed_smc_flash_set_segment()
311 aspeed_smc_error("Tried to change CS%d end address to 0x%" in aspeed_smc_flash_set_segment()
323 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
331 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_flash_set_segment()
345 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); in aspeed_smc_flash_default_read()
346 return 0; in aspeed_smc_flash_default_read()
352 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, in aspeed_smc_flash_default_write()
386 * In read mode, the default SPI command is READ (0x3). In other in aspeed_smc_flash_cmd()
389 * TODO: add support for READ4 (0x13) on AST2600 in aspeed_smc_flash_cmd()
443 aspeed_smc_error("invalid address 0x%08x for CS%d segment : " in aspeed_smc_check_segment_addr()
444 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", in aspeed_smc_check_segment_addr()
456 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; in aspeed_smc_flash_dummies()
457 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; in aspeed_smc_flash_dummies()
479 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); in aspeed_smc_flash_setup()
490 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { in aspeed_smc_flash_setup()
491 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_flash_setup()
500 uint64_t ret = 0; in aspeed_smc_flash_read()
505 for (i = 0; i < size; i++) { in aspeed_smc_flash_read()
506 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
514 for (i = 0; i < size; i++) { in aspeed_smc_flash_read()
515 ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); in aspeed_smc_flash_read()
534 READ = 0x3, READ_4 = 0x13,
535 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
536 DOR = 0x3b, DOR_4 = 0x3c,
537 QOR = 0x6b, QOR_4 = 0x6c,
538 DIOR = 0xbb, DIOR_4 = 0xbc,
539 QIOR = 0xeb, QIOR_4 = 0xec,
541 PP = 0x2, PP_4 = 0x12,
542 DPP = 0xa2,
543 QPP = 0x32, QPP_4 = 0x34,
556 return 0; in aspeed_smc_num_dummies()
582 (uint8_t) data & 0xff); in aspeed_smc_do_snoop()
588 uint8_t cmd = data & 0xff; in aspeed_smc_do_snoop()
595 if (ndummies <= 0) { in aspeed_smc_do_snoop()
606 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); in aspeed_smc_do_snoop()
638 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); in aspeed_smc_flash_write()
648 for (i = 0; i < size; i++) { in aspeed_smc_flash_write()
649 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
656 for (i = 0; i < size; i++) { in aspeed_smc_flash_write()
657 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); in aspeed_smc_flash_write()
692 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ in aspeed_smc_flash_update_ctrl()
720 memset(s->regs, 0, sizeof s->regs); in aspeed_smc_reset()
723 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_reset()
734 qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); in aspeed_smc_reset()
740 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
748 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_reset()
754 s->snoop_dummies = 0; in aspeed_smc_reset()
787 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", in aspeed_smc_read()
797 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 in aspeed_smc_hclk_divisor()
801 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { in aspeed_smc_hclk_divisor()
830 s->regs[s->r_timings] &= ~(0xf << hclk_shift); in aspeed_smc_dma_calibration()
840 cs = 0; in aspeed_smc_dma_calibration()
866 return (delay & 0x7) < 1; in aspeed_smc_inject_read_failure()
868 return (delay & 0x7) < 2; in aspeed_smc_inject_read_failure()
931 s->regs[R_DMA_CHECKSUM] = 0xbadc0de; in aspeed_smc_dma_checksum()
1002 s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff; in aspeed_smc_dma_rw()
1013 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the in aspeed_smc_dma_stop()
1017 s->regs[R_DMA_CHECKSUM] = 0; in aspeed_smc_dma_stop()
1090 if (dma_ctrl == 0xAEED0000) { in aspeed_2600_smc_dma_ctrl()
1097 if (dma_ctrl == 0xDEEA0000) { in aspeed_2600_smc_dma_ctrl()
1138 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1140 s->regs[addr] = value & 0xff; in aspeed_smc_write()
1160 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", in aspeed_smc_write()
1178 for (i = 0; i < asc->cs_num_max; i++) { in aspeed_smc_instance_init()
1206 hwaddr offset = 0; in aspeed_smc_realize()
1243 memory_region_add_subregion(&s->mmio_flash_container, 0x0, in aspeed_smc_realize()
1253 for (i = 0; i < asc->cs_num_max; ++i) { in aspeed_smc_realize()
1292 DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
1339 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1369 uint32_t reg = 0; in aspeed_smc_segment_to_reg()
1383 { 0x10000000, 32 * MiB },
1400 asc->flash_window_base = 0x10000000; in aspeed_2400_smc_class_init()
1401 asc->flash_window_size = 0x6000000; in aspeed_2400_smc_class_init()
1402 asc->features = 0x0; in aspeed_2400_smc_class_init()
1425 { 0x20000000, 64 * MiB }, /* start address is readonly */
1426 { 0x24000000, 32 * MiB },
1427 { 0x26000000, 32 * MiB },
1428 { 0x28000000, 32 * MiB },
1429 { 0x2A000000, 32 * MiB }
1446 asc->segment_addr_mask = 0xffff0000; in aspeed_2400_fmc_class_init()
1448 asc->flash_window_base = 0x20000000; in aspeed_2400_fmc_class_init()
1449 asc->flash_window_size = 0x10000000; in aspeed_2400_fmc_class_init()
1451 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2400_fmc_class_init()
1452 asc->dma_dram_mask = 0x1FFFFFFC; in aspeed_2400_fmc_class_init()
1468 { 0x30000000, 64 * MiB },
1483 asc->r_ce_ctrl = 0xff; in aspeed_2400_spi1_class_init()
1490 asc->flash_window_base = 0x30000000; in aspeed_2400_spi1_class_init()
1491 asc->flash_window_size = 0x10000000; in aspeed_2400_spi1_class_init()
1492 asc->features = 0x0; in aspeed_2400_spi1_class_init()
1513 { 0x20000000, 128 * MiB }, /* start address is readonly */
1514 { 0x28000000, 32 * MiB },
1515 { 0x2A000000, 32 * MiB },
1532 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_fmc_class_init()
1534 asc->flash_window_base = 0x20000000; in aspeed_2500_fmc_class_init()
1535 asc->flash_window_size = 0x10000000; in aspeed_2500_fmc_class_init()
1537 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2500_fmc_class_init()
1538 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2500_fmc_class_init()
1554 { 0x30000000, 32 * MiB }, /* start address is readonly */
1555 { 0x32000000, 96 * MiB }, /* end address is readonly */
1572 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi1_class_init()
1573 asc->flash_window_base = 0x30000000; in aspeed_2500_spi1_class_init()
1574 asc->flash_window_size = 0x8000000; in aspeed_2500_spi1_class_init()
1575 asc->features = 0x0; in aspeed_2500_spi1_class_init()
1590 { 0x38000000, 32 * MiB }, /* start address is readonly */
1591 { 0x3A000000, 96 * MiB }, /* end address is readonly */
1608 asc->segment_addr_mask = 0xffff0000; in aspeed_2500_spi2_class_init()
1609 asc->flash_window_base = 0x38000000; in aspeed_2500_spi2_class_init()
1610 asc->flash_window_size = 0x8000000; in aspeed_2500_spi2_class_init()
1611 asc->features = 0x0; in aspeed_2500_spi2_class_init()
1632 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1637 uint32_t reg = 0; in aspeed_2600_smc_segment_to_reg()
1641 return 0; in aspeed_2600_smc_segment_to_reg()
1661 seg->size = 0; in aspeed_2600_smc_reg_to_segment()
1672 { 0x0, 128 * MiB }, /* start address is readonly */
1674 { 0x0, 0 }, /* disabled */
1691 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_fmc_class_init()
1693 asc->flash_window_base = 0x20000000; in aspeed_2600_fmc_class_init()
1694 asc->flash_window_size = 0x10000000; in aspeed_2600_fmc_class_init()
1697 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_fmc_class_init()
1698 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_fmc_class_init()
1714 { 0x0, 128 * MiB }, /* start address is readonly */
1715 { 0x0, 0 }, /* disabled */
1732 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi1_class_init()
1733 asc->flash_window_base = 0x30000000; in aspeed_2600_spi1_class_init()
1734 asc->flash_window_size = 0x10000000; in aspeed_2600_spi1_class_init()
1737 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi1_class_init()
1738 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi1_class_init()
1754 { 0x0, 128 * MiB }, /* start address is readonly */
1755 { 0x0, 0 }, /* disabled */
1756 { 0x0, 0 }, /* disabled */
1773 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_2600_spi2_class_init()
1774 asc->flash_window_base = 0x50000000; in aspeed_2600_spi2_class_init()
1775 asc->flash_window_size = 0x10000000; in aspeed_2600_spi2_class_init()
1778 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2600_spi2_class_init()
1779 asc->dma_dram_mask = 0x3FFFFFFC; in aspeed_2600_spi2_class_init()
1798 #define AST1030_SEG_ADDR_MASK 0x0ff80000
1803 uint32_t reg = 0; in aspeed_1030_smc_segment_to_reg()
1807 return 0; in aspeed_1030_smc_segment_to_reg()
1827 seg->size = 0; in aspeed_1030_smc_reg_to_segment()
1837 { 0x0, 128 * MiB }, /* start address is readonly */
1839 { 0x0, 0 }, /* disabled */
1856 asc->segment_addr_mask = 0x0ff80ff8; in aspeed_1030_fmc_class_init()
1858 asc->flash_window_base = 0x80000000; in aspeed_1030_fmc_class_init()
1859 asc->flash_window_size = 0x10000000; in aspeed_1030_fmc_class_init()
1861 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_fmc_class_init()
1862 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_fmc_class_init()
1878 { 0x0, 128 * MiB }, /* start address is readonly */
1879 { 0x0, 0 }, /* disabled */
1896 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi1_class_init()
1897 asc->flash_window_base = 0x90000000; in aspeed_1030_spi1_class_init()
1898 asc->flash_window_size = 0x10000000; in aspeed_1030_spi1_class_init()
1900 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi1_class_init()
1901 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi1_class_init()
1916 { 0x0, 128 * MiB }, /* start address is readonly */
1917 { 0x0, 0 }, /* disabled */
1934 asc->segment_addr_mask = 0x0ff00ff0; in aspeed_1030_spi2_class_init()
1935 asc->flash_window_base = 0xb0000000; in aspeed_1030_spi2_class_init()
1936 asc->flash_window_size = 0x10000000; in aspeed_1030_spi2_class_init()
1938 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_1030_spi2_class_init()
1939 asc->dma_dram_mask = 0x000BFFFC; in aspeed_1030_spi2_class_init()
1958 #define AST2700_SEG_ADDR_MASK 0xffff0000
1963 uint32_t reg = 0; in aspeed_2700_smc_segment_to_reg()
1967 return 0; in aspeed_2700_smc_segment_to_reg()
1987 seg->size = 0; in aspeed_2700_smc_reg_to_segment()
1994 [R_CE_CTRL] = 0x0000aa00,
1995 [R_CTRL0] = 0x406b0641,
1996 [R_CTRL1] = 0x00000400,
1997 [R_CTRL2] = 0x00000400,
1998 [R_CTRL3] = 0x00000400,
1999 [R_SEG_ADDR0] = 0x08000000,
2000 [R_SEG_ADDR1] = 0x10000800,
2001 [R_SEG_ADDR2] = 0x00000000,
2002 [R_SEG_ADDR3] = 0x00000000,
2003 [R_DUMMY_DATA] = 0x00010000,
2004 [R_DMA_DRAM_ADDR_HIGH] = 0x00000000,
2005 [R_TIMINGS] = 0x007b0000,
2019 { 0x0, 128 * MiB }, /* start address is readonly */
2022 { 0x0, 0 }, /* disabled */
2039 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_fmc_class_init()
2041 asc->flash_window_base = 0x100000000; in aspeed_2700_fmc_class_init()
2045 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_fmc_class_init()
2046 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_fmc_class_init()
2062 { 0x0, 128 * MiB }, /* start address is readonly */
2064 { 0x0, 0 }, /* disabled */
2081 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi0_class_init()
2082 asc->flash_window_base = 0x180000000; in aspeed_2700_spi0_class_init()
2086 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi0_class_init()
2087 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi0_class_init()
2103 { 0x0, 128 * MiB }, /* start address is readonly */
2104 { 0x0, 0 }, /* disabled */
2121 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi1_class_init()
2122 asc->flash_window_base = 0x200000000; in aspeed_2700_spi1_class_init()
2126 asc->dma_flash_mask = 0x2FFFFFFC; in aspeed_2700_spi1_class_init()
2127 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi1_class_init()
2143 { 0x0, 128 * MiB }, /* start address is readonly */
2144 { 0x0, 0 }, /* disabled */
2161 asc->segment_addr_mask = 0xffffffff; in aspeed_2700_spi2_class_init()
2162 asc->flash_window_base = 0x280000000; in aspeed_2700_spi2_class_init()
2166 asc->dma_flash_mask = 0x0FFFFFFC; in aspeed_2700_spi2_class_init()
2167 asc->dma_dram_mask = 0xFFFFFFFC; in aspeed_2700_spi2_class_init()