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/linux-3.3/arch/arm/boot/dts/
Dprima2-cb.dts10 reg = <0x00000000 0x20000000>;
20 #size-cells = <0>;
22 cpu@0 {
23 reg = <0x0>;
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
43 reg = <0x80040000 0x1000>;
47 arm,filter-ranges = <0 0x40000000>;
[all …]
Dpicoxcell-pc3x2.dtsi22 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
40 pclk: clock@0 {
52 ranges = <0 0x80000000 0x400000>;
56 reg = <0x30000 0x10000>;
62 reg = <0x40000 0x10000>;
68 reg = <0x50000 0x10000>;
75 reg = <0x60000 0x1000>;
82 reg = <0x64000 0x1000>;
[all …]
Dpicoxcell-pc3x3.dtsi22 #size-cells = <0>;
24 cpu@0 {
27 reg = <0>;
42 #size-cells = <0>;
43 reg = <0x800a0048 4>;
46 tzprot_clk: clock@0 {
49 picochip,clk-disable-bit = <0>;
129 reg = <0x800a0050 0x8>;
148 ranges = <0 0x80000000 0x400000>;
152 reg = <0x30000 0x10000>;
[all …]
/linux-3.3/drivers/mtd/chips/
Djedec_probe.c26 #define AM29DL800BB 0x22CB
27 #define AM29DL800BT 0x224A
29 #define AM29F800BB 0x2258
30 #define AM29F800BT 0x22D6
31 #define AM29LV400BB 0x22BA
32 #define AM29LV400BT 0x22B9
33 #define AM29LV800BB 0x225B
34 #define AM29LV800BT 0x22DA
35 #define AM29LV160DT 0x22C4
36 #define AM29LV160DB 0x2249
[all …]
/linux-3.3/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hdr.h39 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
40 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
41 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
42 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
43 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
44 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
45 NETXEN_HW_H6_CH_HUB_ADR = 0x08
48 /* Hub 0 */
50 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
51 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/linux-3.3/arch/powerpc/boot/dts/
Dp2020ds.dts23 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
24 0x1 0x0 0x0 0xe0000000 0x08000000
25 0x2 0x0 0x0 0xffa00000 0x00040000
26 0x3 0x0 0x0 0xffdf0000 0x00008000
27 0x4 0x0 0x0 0xffa40000 0x00040000
28 0x5 0x0 0x0 0xffa80000 0x00040000
29 0x6 0x0 0x0 0xffac0000 0x00040000>;
30 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xffe00000 0x100000>;
38 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
Dmpc8544ds.dts20 reg = <0 0 0 0>; // Filled by U-Boot
24 reg = <0 0xe0005000 0 0x1000>;
28 ranges = <0x0 0x0 0xe0000000 0x100000>;
32 reg = <0 0xe0008000 0 0x1000>;
33 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
34 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
36 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
39 /* IDSEL 0x11 J17 Slot 1 */
40 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
41 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
[all …]
Dvirtex440-ml507.dts29 DDR2_SDRAM: memory@0 {
31 reg = < 0 0x10000000 >;
40 #size-cells = <0>;
41 ppc440_0: cpu@0 {
44 d-cache-line-size = <0x20>;
45 d-cache-size = <0x8000>;
49 i-cache-line-size = <0x20>;
50 i-cache-size = <0x8000>;
52 reg = <0>;
55 xlnx,apu-udi-0 = <0>;
[all …]
Dmpc8572ds_36b.dts23 reg = <0xf 0xffe05000 0 0x1000>;
25 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
26 0x1 0x0 0xf 0xe0000000 0x08000000
27 0x2 0x0 0xf 0xffa00000 0x00040000
28 0x3 0x0 0xf 0xffdf0000 0x00008000
29 0x4 0x0 0xf 0xffa40000 0x00040000
30 0x5 0x0 0xf 0xffa80000 0x00040000
31 0x6 0x0 0xf 0xffac0000 0x00040000>;
35 ranges = <0x0 0xf 0xffe00000 0x100000>;
39 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
Dmpc8572ds.dts23 reg = <0 0xffe05000 0 0x1000>;
25 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
26 0x1 0x0 0x0 0xe0000000 0x08000000
27 0x2 0x0 0x0 0xffa00000 0x00040000
28 0x3 0x0 0x0 0xffdf0000 0x00008000
29 0x4 0x0 0x0 0xffa40000 0x00040000
30 0x5 0x0 0x0 0xffa80000 0x00040000
31 0x6 0x0 0x0 0xffac0000 0x00040000>;
35 ranges = <0x0 0 0xffe00000 0x100000>;
39 reg = <0 0xffe08000 0 0x1000>;
[all …]
Dmotionpro.dts82 reg = <0x68>;
88 reg = <0x8000 0x4000>;
97 ranges = <0 0 0xff000000 0x01000000
98 1 0 0x50000000 0x00010000
99 2 0 0x50010000 0x00010000
100 3 0 0x50020000 0x00010000>;
103 kollmorgen@1,0 {
105 reg = <1 0 0x10000>;
106 interrupts = <1 1 0>;
110 cpld@2,0 {
[all …]
Dvirtex440-ml510.dts18 DDR2_SDRAM_DIMM0: memory@0 {
20 reg = < 0x0 0x20000000 >;
28 linux,stdout-path = "/plb@0/serial@83e00000";
32 #cpus = <0x1>;
33 #size-cells = <0>;
34 ppc440_0: cpu@0 {
39 d-cache-line-size = <0x20>;
40 d-cache-size = <0x8000>;
44 i-cache-line-size = <0x20>;
45 i-cache-size = <0x8000>;
[all …]
/linux-3.3/drivers/mtd/maps/
Dautcpu12-nvram.c41 .phys = 0x12000000,
48 autcpu12_sram_map.virt = ioremap(0x12000000, SZ_128K); in init_autcpu12_sram()
58 * read ofs 0 in init_autcpu12_sram()
59 * read ofs 0x10000 in init_autcpu12_sram()
60 * Write complement to ofs 0x100000 in init_autcpu12_sram()
61 * Read and check result on ofs 0x0 in init_autcpu12_sram()
64 save0 = map_read32(&autcpu12_sram_map,0); in init_autcpu12_sram()
65 save1 = map_read32(&autcpu12_sram_map,0x10000); in init_autcpu12_sram()
66 map_write32(&autcpu12_sram_map,~save0,0x10000); in init_autcpu12_sram()
67 /* if we find this pattern on 0x0, we have 32K size in init_autcpu12_sram()
[all …]
/linux-3.3/drivers/media/dvb/b2c2/
Dflexcop-sram.c27 return 0; in flexcop_sram_init()
54 return 0; in flexcop_sram_set_dest()
74 #if 0
80 for (i = 0; i < len; i++) {
81 command = bank | addr | 0x04000000 | (*buf << 0x10);
85 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
90 if (retries == 0)
93 write_reg_dw(adapter, 0x700, command);
105 for (i = 0; i < len; i++) {
106 command = bank | addr | 0x04008000;
[all …]
/linux-3.3/arch/mips/lantiq/xway/
Dmach-easy50601.c24 .offset = 0x0,
25 .size = 0x10000,
29 .offset = 0x10000,
30 .size = 0x10000,
34 .offset = 0x20000,
35 .size = 0xE0000,
39 .offset = 0x100000,
40 .size = 0x300000,
Dmach-easy50712.c26 .offset = 0x0,
27 .size = 0x10000,
31 .offset = 0x10000,
32 .size = 0x10000,
36 .offset = 0x20000,
37 .size = 0xe0000,
41 .offset = 0x100000,
42 .size = 0x300000,
/linux-3.3/arch/arm/mach-exynos/include/mach/
Dmap.h19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
22 #define S3C_UART_OFFSET (0x10000)
26 #define EXYNOS4_PA_SYSRAM0 0x02025000
27 #define EXYNOS4_PA_SYSRAM1 0x02020000
29 #define EXYNOS4_PA_FIMC0 0x11800000
30 #define EXYNOS4_PA_FIMC1 0x11810000
31 #define EXYNOS4_PA_FIMC2 0x11820000
32 #define EXYNOS4_PA_FIMC3 0x11830000
34 #define EXYNOS4_PA_I2S0 0x03830000
35 #define EXYNOS4_PA_I2S1 0xE3100000
[all …]
/linux-3.3/arch/arm/mach-s3c2443/
Dmach-smdk2443.c56 .length = 0x10000,
59 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
66 .length = 0x10000,
69 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
81 [0] = {
82 .hwport = 0,
83 .flags = 0,
84 .ucon = 0x3c5,
85 .ulcon = 0x03,
86 .ufcon = 0x51,
[all …]
/linux-3.3/arch/arm/mach-s3c2440/
Dmach-smdk2440.c58 .length = 0x10000,
61 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
68 .length = 0x10000,
71 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
83 [0] = {
84 .hwport = 0,
85 .flags = 0,
86 .ucon = 0x3c5,
87 .ulcon = 0x03,
88 .ufcon = 0x51,
[all …]
/linux-3.3/arch/mips/include/asm/mips-boards/
Dmalta.h29 #define MIPS_MSC01_IC_REG_BASE 0x1bc40000
30 #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
37 #define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
44 return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); in get_gt_port_base()
51 return (unsigned long) ioremap(addr, 0x10000); in get_msc_port_base()
57 #define GCMP_BASE_ADDR 0x1fbf8000
63 #define GIC_BASE_ADDR 0x1bdc0000
70 #define MSC01_BIU_REG_BASE 0x1bc80000
72 #define MSC01_SC_CFG_OFS 0x0110
73 #define MSC01_SC_CFG_GICPRES_MSK 0x00000004
[all …]
/linux-3.3/arch/mips/include/asm/ip32/
Dmace.h18 #define MACE_BASE 0x1f000000 /* physical */
43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST 0
45 #define MACEPCI_ERROR_DEVSEL_MED 0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
48 #define MACEPCI_ERROR_66MHZ BIT(0)
51 #define MACEPCI_CONTROL_INT_MASK 0xff
61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
71 unsigned int _pad[0xcf8/4 - 4];
79 #define MACEPCI_LOW_MEMORY 0x1a000000
[all …]
/linux-3.3/drivers/staging/rtl8192e/rtl8192e/
Dr819xE_phyreg.h5 #define RF_DATA 0x1d4 // FW will write RF data in the register.
9 #define rPMAC_Reset 0x100
10 #define rPMAC_TxStart 0x104
11 #define rPMAC_TxLegacySIG 0x108
12 #define rPMAC_TxHTSIG1 0x10c
13 #define rPMAC_TxHTSIG2 0x110
14 #define rPMAC_PHYDebug 0x114
15 #define rPMAC_TxPacketNum 0x118
16 #define rPMAC_TxIdle 0x11c
17 #define rPMAC_TxMACHeader0 0x120
[all …]
Dr8192E_phyreg.h23 #define RF_DATA 0x1d4
25 #define rPMAC_Reset 0x100
26 #define rPMAC_TxStart 0x104
27 #define rPMAC_TxLegacySIG 0x108
28 #define rPMAC_TxHTSIG1 0x10c
29 #define rPMAC_TxHTSIG2 0x110
30 #define rPMAC_PHYDebug 0x114
31 #define rPMAC_TxPacketNum 0x118
32 #define rPMAC_TxIdle 0x11c
33 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-3.3/drivers/staging/rtl8192u/
Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 // FW will write RF data in the register.
9 #define rPMAC_Reset 0x100
10 #define rPMAC_TxStart 0x104
11 #define rPMAC_TxLegacySIG 0x108
12 #define rPMAC_TxHTSIG1 0x10c
13 #define rPMAC_TxHTSIG2 0x110
14 #define rPMAC_PHYDebug 0x114
15 #define rPMAC_TxPacketNum 0x118
16 #define rPMAC_TxIdle 0x11c
17 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-3.3/arch/arm/mach-s3c2416/
Dmach-smdk2416.c66 .length = 0x10000,
69 .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
76 .length = 0x10000,
79 .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
97 [0] = {
98 .hwport = 0,
99 .flags = 0,
106 .flags = 0,
114 .flags = 0,
116 .ulcon = ULCON | 0x50,
[all …]

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