1 /* linux/arch/arm/mach-exynos/include/mach/map.h 2 * 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com/ 5 * 6 * EXYNOS4 - Memory map definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_MAP_H 14 #define __ASM_ARCH_MAP_H __FILE__ 15 16 #include <plat/map-base.h> 17 18 /* 19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. 20 * So need to define it, and here is to avoid redefinition warning. 21 */ 22 #define S3C_UART_OFFSET (0x10000) 23 24 #include <plat/map-s5p.h> 25 26 #define EXYNOS4_PA_SYSRAM0 0x02025000 27 #define EXYNOS4_PA_SYSRAM1 0x02020000 28 29 #define EXYNOS4_PA_FIMC0 0x11800000 30 #define EXYNOS4_PA_FIMC1 0x11810000 31 #define EXYNOS4_PA_FIMC2 0x11820000 32 #define EXYNOS4_PA_FIMC3 0x11830000 33 34 #define EXYNOS4_PA_I2S0 0x03830000 35 #define EXYNOS4_PA_I2S1 0xE3100000 36 #define EXYNOS4_PA_I2S2 0xE2A00000 37 38 #define EXYNOS4_PA_PCM0 0x03840000 39 #define EXYNOS4_PA_PCM1 0x13980000 40 #define EXYNOS4_PA_PCM2 0x13990000 41 42 #define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) 43 44 #define EXYNOS4_PA_ONENAND 0x0C000000 45 #define EXYNOS4_PA_ONENAND_DMA 0x0C600000 46 47 #define EXYNOS4_PA_CHIPID 0x10000000 48 49 #define EXYNOS4_PA_SYSCON 0x10010000 50 #define EXYNOS4_PA_PMU 0x10020000 51 #define EXYNOS4_PA_CMU 0x10030000 52 53 #define EXYNOS4_PA_SYSTIMER 0x10050000 54 #define EXYNOS4_PA_WATCHDOG 0x10060000 55 #define EXYNOS4_PA_RTC 0x10070000 56 57 #define EXYNOS4_PA_KEYPAD 0x100A0000 58 59 #define EXYNOS4_PA_DMC0 0x10400000 60 61 #define EXYNOS4_PA_COMBINER 0x10440000 62 63 #define EXYNOS4_PA_GIC_CPU 0x10480000 64 #define EXYNOS4_PA_GIC_DIST 0x10490000 65 66 #define EXYNOS4_PA_COREPERI 0x10500000 67 #define EXYNOS4_PA_TWD 0x10500600 68 #define EXYNOS4_PA_L2CC 0x10502000 69 70 #define EXYNOS4_PA_MDMA 0x10810000 71 #define EXYNOS4_PA_PDMA0 0x12680000 72 #define EXYNOS4_PA_PDMA1 0x12690000 73 74 #define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000 75 #define EXYNOS4_PA_SYSMMU_SSS 0x10A50000 76 #define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000 77 #define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000 78 #define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000 79 #define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000 80 #define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000 81 #define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000 82 #define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000 83 #define EXYNOS4_PA_SYSMMU_PCIe 0x12620000 84 #define EXYNOS4_PA_SYSMMU_G2D 0x12A20000 85 #define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000 86 #define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000 87 #define EXYNOS4_PA_SYSMMU_TV 0x12E20000 88 #define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 89 #define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 90 #define EXYNOS4_PA_SPI0 0x13920000 91 #define EXYNOS4_PA_SPI1 0x13930000 92 #define EXYNOS4_PA_SPI2 0x13940000 93 94 95 #define EXYNOS4_PA_GPIO1 0x11400000 96 #define EXYNOS4_PA_GPIO2 0x11000000 97 #define EXYNOS4_PA_GPIO3 0x03860000 98 99 #define EXYNOS4_PA_MIPI_CSIS0 0x11880000 100 #define EXYNOS4_PA_MIPI_CSIS1 0x11890000 101 102 #define EXYNOS4_PA_FIMD0 0x11C00000 103 104 #define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 105 #define EXYNOS4_PA_DWMCI 0x12550000 106 107 #define EXYNOS4_PA_SATA 0x12560000 108 #define EXYNOS4_PA_SATAPHY 0x125D0000 109 #define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 110 111 #define EXYNOS4_PA_SROMC 0x12570000 112 113 #define EXYNOS4_PA_EHCI 0x12580000 114 #define EXYNOS4_PA_OHCI 0x12590000 115 #define EXYNOS4_PA_HSPHY 0x125B0000 116 #define EXYNOS4_PA_MFC 0x13400000 117 118 #define EXYNOS4_PA_UART 0x13800000 119 120 #define EXYNOS4_PA_VP 0x12C00000 121 #define EXYNOS4_PA_MIXER 0x12C10000 122 #define EXYNOS4_PA_SDO 0x12C20000 123 #define EXYNOS4_PA_HDMI 0x12D00000 124 #define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 125 126 #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 127 128 #define EXYNOS4_PA_ADC 0x13910000 129 #define EXYNOS4_PA_ADC1 0x13911000 130 131 #define EXYNOS4_PA_AC97 0x139A0000 132 133 #define EXYNOS4_PA_SPDIF 0x139B0000 134 135 #define EXYNOS4_PA_TIMER 0x139D0000 136 137 #define EXYNOS4_PA_SDRAM 0x40000000 138 139 /* Compatibiltiy Defines */ 140 141 #define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0) 142 #define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1) 143 #define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2) 144 #define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3) 145 #define S3C_PA_IIC EXYNOS4_PA_IIC(0) 146 #define S3C_PA_IIC1 EXYNOS4_PA_IIC(1) 147 #define S3C_PA_IIC2 EXYNOS4_PA_IIC(2) 148 #define S3C_PA_IIC3 EXYNOS4_PA_IIC(3) 149 #define S3C_PA_IIC4 EXYNOS4_PA_IIC(4) 150 #define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) 151 #define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) 152 #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 153 #define S3C_PA_RTC EXYNOS4_PA_RTC 154 #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 155 #define S3C_PA_UART EXYNOS4_PA_UART 156 #define S3C_PA_SPI0 EXYNOS4_PA_SPI0 157 #define S3C_PA_SPI1 EXYNOS4_PA_SPI1 158 #define S3C_PA_SPI2 EXYNOS4_PA_SPI2 159 160 #define S5P_PA_EHCI EXYNOS4_PA_EHCI 161 #define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0 162 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 163 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 164 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 165 #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 166 #define S5P_PA_HDMI EXYNOS4_PA_HDMI 167 #define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY 168 #define S5P_PA_MFC EXYNOS4_PA_MFC 169 #define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 170 #define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 171 #define S5P_PA_MIXER EXYNOS4_PA_MIXER 172 #define S5P_PA_ONENAND EXYNOS4_PA_ONENAND 173 #define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 174 #define S5P_PA_SDO EXYNOS4_PA_SDO 175 #define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 176 #define S5P_PA_VP EXYNOS4_PA_VP 177 178 #define SAMSUNG_PA_ADC EXYNOS4_PA_ADC 179 #define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1 180 #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD 181 182 /* Compatibility UART */ 183 184 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 185 186 #define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) 187 #define S5P_PA_UART0 S5P_PA_UART(0) 188 #define S5P_PA_UART1 S5P_PA_UART(1) 189 #define S5P_PA_UART2 S5P_PA_UART(2) 190 #define S5P_PA_UART3 S5P_PA_UART(3) 191 #define S5P_PA_UART4 S5P_PA_UART(4) 192 193 #define S5P_SZ_UART SZ_256 194 195 #endif /* __ASM_ARCH_MAP_H */ 196