dvb/b2c2/flexcop-sram.c

27 	return 0;  in flexcop_sram_init()
54 	return 0;  in flexcop_sram_set_dest()
74 #if 0
80 	for (i = 0; i < len; i++) {
81 		command = bank | addr | 0x04000000 | (*buf << 0x10);
85 		while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
90 		if (retries == 0)
93 		write_reg_dw(adapter, 0x700, command);
105 	for (i = 0; i < len; i++) {
106 		command = bank | addr | 0x04008000;
110 		while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
115 		if (retries == 0)
118 		write_reg_dw(adapter, 0x700, command);
122 		while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
127 		if (retries == 0)
130 		value = read_reg_dw(adapter, 0x700) >> 0x10;
132 		*buf = (value & 0xff);
143 	bank = 0;
145 	if (adapter->dw_sram_type == 0x20000) {
146 		bank = (addr & 0x18000) << 0x0d;
149 	if (adapter->dw_sram_type == 0x00000) {
150 		if ((addr >> 0x0f) == 0)
151 			bank = 0x20000000;
153 			bank = 0x10000000;
155 	flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);
161 	bank = 0;
163 	if (adapter->dw_sram_type == 0x20000) {
164 		bank = (addr & 0x18000) << 0x0d;
167 	if (adapter->dw_sram_type == 0x00000) {
168 		if ((addr >> 0x0f) == 0)
169 			bank = 0x20000000;
171 			bank = 0x10000000;
173 	flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);
179 	while (len != 0) {
184 		if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
185 			length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
198 	while (len != 0) {
204 		if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
205 			length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
217 	write_reg_dw(adapter, 0x71c,
218 			(mask | (~0x30000 & read_reg_dw(adapter, 0x71c))));
224 	tmp = read_reg_dw(adapter, 0x71c);
225 	write_reg_dw(adapter, 0x71c, 1);
227 	if (read_reg_dw(adapter, 0x71c) != 0) {
228 		write_reg_dw(adapter, 0x71c, tmp);
229 		adapter->dw_sram_type = tmp & 0x30000;
232 		adapter->dw_sram_type = 0x10000;
245 	tmp2 = 0xa5;
246 	tmp1 = 0x4f;
251 	tmp2 = 0;
257 	dprintk("%s: wrote 0xa5, read 0x%2x\n", __func__, tmp2);
259 	if (tmp2 != 0xa5)
260 		return 0;
262 	tmp2 = 0x5a;
263 	tmp1 = 0xf4;
268 	tmp2 = 0;
274 	dprintk("%s: wrote 0x5a, read 0x%2x\n", __func__, tmp2);
276 	if (tmp2 != 0x5a)
277 		return 0;
283 	if (adapter->dw_sram_type == 0x10000)
285 	if (adapter->dw_sram_type == 0x00000)
287 	if (adapter->dw_sram_type == 0x20000)
293    - for 128K there are 4x32K chips at bank 0,1,2,3.
295    - for  32K there is one 32K chip at bank 0.
298    by bits 28-29 of the 0x700 register.
300    bank 0 covers addresses 0x00000-0x07fff
301    bank 1 covers addresses 0x08000-0x0ffff
302    bank 2 covers addresses 0x10000-0x17fff
303    bank 3 covers addresses 0x18000-0x1ffff */
312 	write_reg_dw(adapter, 0x71c, 1);
313 	tmp3 = read_reg_dw(adapter, 0x71c);
315 	write_reg_dw(adapter, 0x71c, tmp2);
319 	if (tmp3 != 0) {
320 		sram_set_size(adapter, 0x10000);
322 		write_reg_dw(adapter, 0x208, tmp);
327 	if (sram_test_location(adapter, 0x20000, 0x18000) != 0) {
328 		sram_set_size(adapter, 0x20000);
330 		write_reg_dw(adapter, 0x208, tmp);
335 	if (sram_test_location(adapter, 0x00000, 0x10000) != 0) {
336 		sram_set_size(adapter, 0x00000);
338 		write_reg_dw(adapter, 0x208, tmp);
343 	if (sram_test_location(adapter, 0x10000, 0x00000) != 0) {
344 		sram_set_size(adapter, 0x10000);
346 		write_reg_dw(adapter, 0x208, tmp);
351 	sram_set_size(adapter, 0x10000);
353 	write_reg_dw(adapter, 0x208, tmp);
355 	return 0;