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/linux-6.8/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux-6.8/mm/
Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/backing-dev.h>
39 #include <linux/memory-tiers.h>
42 #include <asm/tlb.h>
93 if (!vma->vm_mm) /* vdso */ in __thp_vma_allowable_orders()
102 test_bit(MMF_DISABLE_THP, &vma->vm_mm->flags)) in __thp_vma_allowable_orders()
134 addr = vma->vm_end - (PAGE_SIZE << order); in __thp_vma_allowable_orders()
149 if (!in_pf && shmem_file(vma->vm_file)) in __thp_vma_allowable_orders()
150 return shmem_is_huge(file_inode(vma->vm_file), vma->vm_pgoff, in __thp_vma_allowable_orders()
151 !enforce_sysfs, vma->vm_mm, vm_flags) in __thp_vma_allowable_orders()
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Dmapping_dirty_helpers.c1 // SPDX-License-Identifier: GPL-2.0
11 * struct wp_walk - Private struct for pagetable walk callbacks
25 * wp_pte - Write-protect a pte
31 * The function write-protects a pte and records the range in
32 * virtual address space of touched ptes for efficient range TLB flushes.
37 struct wp_walk *wpwalk = walk->private; in wp_pte()
41 pte_t old_pte = ptep_modify_prot_start(walk->vma, addr, pte); in wp_pte()
44 ptep_modify_prot_commit(walk->vma, addr, pte, old_pte, ptent); in wp_pte()
45 wpwalk->total++; in wp_pte()
46 wpwalk->tlbflush_start = min(wpwalk->tlbflush_start, addr); in wp_pte()
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Dmprotect.c1 // SPDX-License-Identifier: GPL-2.0
34 #include <linux/memory-tiers.h>
38 #include <asm/tlb.h>
47 if (WARN_ON_ONCE(!(vma->vm_flags & VM_WRITE))) in can_change_pte_writable()
58 /* Do we need write faults for uffd-wp tracking? */ in can_change_pte_writable()
62 if (!(vma->vm_flags & VM_SHARED)) { in can_change_pte_writable()
64 * Writable MAP_PRIVATE mapping: We can only special-case on in can_change_pte_writable()
66 * write-fault handler similarly would map them writable without in can_change_pte_writable()
75 * needs a real write-fault for writenotify in can_change_pte_writable()
78 * just like the write-fault handler would do. in can_change_pte_writable()
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Dmadvise.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/page-isolation.h>
28 #include <linux/backing-dev.h>
35 #include <asm/tlb.h>
41 struct mmu_gather *tlb; member
46 * Any behaviour which results in changes to the vma->vm_flags needs to
76 /* Add 1 for NUL terminator at the end of the anon_name->name */ in anon_vma_name_alloc()
80 kref_init(&anon_name->kref); in anon_vma_name_alloc()
81 memcpy(anon_name->name, name, count); in anon_vma_name_alloc()
96 mmap_assert_locked(vma->vm_mm); in anon_vma_name()
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/linux-6.8/Documentation/admin-guide/mm/
Dtranshuge.rst26 requiring larger clear-page copy-page in page faults which is a
36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
48 Modern kernels support "multi-size THP" (mTHP), which introduces the
50 but smaller than traditional PMD-size (as described above), in
51 increments of a power-of-2 number of pages. mTHP can back anonymous
53 PTE-mapped, but in many cases can still provide similar benefits to
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/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux-6.8/arch/arm/mm/
Dtlb-v4wb.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs w/o I TLB entry, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
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Dtlb-v4wbi.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 and version 5 TLB handling functions.
8 * These assume a split I/D TLBs, with a write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
22 * Invalidate a range of TLB entries in the specified address space.
24 * - start - range start address
25 * - end - range end address
26 * - mm - mm_struct describing address space
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Dtlb-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
8 * ARM architecture version 6 TLB handling functions.
9 * These assume a split I/D TLB.
14 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
19 .arch armv7-a
24 * Invalidate a range of TLB entries in the specified address space.
26 * - start - start address (may not be aligned)
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Dtlb-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 6 TLB handling functions.
8 * These assume a split I/D TLB.
12 #include <asm/asm-offsets.h>
16 #include "proc-macros.S"
25 * Invalidate a range of TLB entries in the specified address space.
27 * - start - start address (may not be aligned)
28 * - end - end address (exclusive, may not be aligned)
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Dtlb-v4.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2002 Russell King
7 * ARM architecture version 4 TLB handling functions.
8 * These assume a split I/D TLBs, and no write buffer.
15 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
23 * Invalidate a range of TLB entries in the specified user address space.
25 * - start - range start address
26 * - end - range end address
27 * - mm - mm_struct describing address space
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/linux-6.8/arch/mips/mm/
Dtlbex.c6 * Synthesize TLB refill handlers at runtime.
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
34 #include <asm/cpu-type.h>
52 * TLB load/store/modify handlers.
131 * CVMSEG starts at address -32768 and extends for in scratchpad_offset()
135 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; in scratchpad_offset()
230 * TLB exception handlers.
262 unsigned int count = (end - start) / sizeof(u32); in dump_handler()
279 /* The only general purpose registers allowed in TLB handlers. */
307 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
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/linux-6.8/arch/sh/mm/
Dtlb-pteaex.c2 * arch/sh/mm/tlb-pteaex.c
4 * TLB operations for SH-X3 CPUs featuring PTE ASID Extensions.
25 if (vma && current->active_mm != vma->vm_mm) in __update_tlb()
42 * For the extended mode TLB this is trivial, only the ESZ and in __update_tlb()
44 * the protection bits (with the exception of the compat-mode SZ in __update_tlb()
58 /* Load the TLB */ in __update_tlb()
64 * While SH-X2 extended TLB mode splits out the memory-mapped I/UTLB
65 * data arrays, SH-X3 cores with PTEAEX split out the memory-mapped
67 * in extended mode, the legacy 8-bit ASID field in address array 1 has
86 * Flush all the TLB. in local_flush_tlb_all()
/linux-6.8/arch/arc/include/asm/
Dpgalloc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -"/proc/meminfo | grep PageTables" kept on increasing
10 * -Variable pg-sz means that Page Tables could be variable sized themselves
11 * So calculate it based on addr traversal split [pgd-bits:pte-bits:xxx]
12 * -Page Table size capped to max 1 to save memory - hence verified.
13 * -Since these deal with constants, gcc compile-time optimizes them.
16 * -Added pgtable ctor/dtor used for pgtable mem accounting
19 * -Switched pgtable_t from being struct page * to unsigned long
24 * pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate)
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/linux-6.8/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.8/arch/arm64/include/asm/
Dkvm_pgtable.h1 // SPDX-License-Identifier: GPL-2.0-only
14 #define KVM_PGTABLE_FIRST_LEVEL -1
18 * The largest supported block sizes for KVM (no 52-bit PA support):
19 * - 4K (level 1): 1GB
20 * - 16K (level 2): 32MB
21 * - 64K (level 2): 512MB
60 #define KVM_PHYS_INVALID (-1ULL)
142 * struct kvm_pgtable_mm_ops - Memory management callbacks.
184 * enum kvm_pgtable_stage2_flags - Stage-2 page-table flags.
185 * @KVM_PGTABLE_S2_NOFWB: Don't enforce Normal-WB even if the CPUs have
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/linux-6.8/tools/perf/pmu-events/arch/x86/alderlake/
Dcache.json14 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
61 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
98 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
104 …"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MI…
107 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
125 …quests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses t…
187 …ublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss exc…
201 …"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.…
204 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
213 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
[all …]
/linux-6.8/include/linux/
Dio-pgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
28 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
29 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
32 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
33 * single page. IOMMUs that cannot batch TLB invalidation
50 * struct io_pgtable_cfg - Configuration data for a set of page tables.
53 * action by the low-level page table allocator.
60 * @tlb: TLB management callbacks for this set of tables.
68 * even in non-secure state where they should normally be ignored.
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/linux-6.8/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.8/tools/perf/pmu-events/arch/x86/meteorlake/
Dcache.json14 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
52 …-demand loads and gets hit at least once by demand. The valid outstanding interval is defined unti…
86 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
89 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
98 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
113 …"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MIS…
116 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
134 …quests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses t…
205 …ublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss exc…
228 …"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.M…
[all …]
/linux-6.8/arch/mips/kvm/
Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
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/linux-6.8/Documentation/admin-guide/hw-vuln/
Dmultihit.rst6 instruction fetch hits multiple entries in the instruction TLB. This can
13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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