| /linux/fs/befs/ |
| H A D | datastream.c | 187 /* Size of indirect block */ in befs_count_blocks()
189 metablocks += ds->indirect.len; in befs_count_blocks()
192 * Double indir block, plus all the indirect blocks it maps. in befs_count_blocks()
193 * In the double-indirect range, all block runs of data are in befs_count_blocks()
195 * how many data block runs are in the double-indirect region, in befs_count_blocks()
196 * and from that we know how many indirect blocks it takes to in befs_count_blocks()
197 * map them. We assume that the indirect blocks are also in befs_count_blocks()
243 * as in the indirect region code).
291 * blockno is in the indirect region of the datastream.
297 * For each block in the indirect run of the datastream, read
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | branch.json | 24 …"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch tha…
27 …"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that…
30 …"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts wh…
33 …"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts whe…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
42 …"PublicDescription": "Indirect branch with predicted address executed. This event counts when any …
45 …"BriefDescription": "Indirect branch with predicted address executed. This event counts when any i…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | branch.json | 24 …"PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whi…
27 …"BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whic…
30 …"PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts w…
33 …"BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts wh…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
42 …"PublicDescription": "Indirect branch with predicted address executed.This event counts when any i…
45 …"BriefDescription": "Indirect branch with predicted address executed.This event counts when any in…
|
| /linux/fs/minix/ |
| H A D | itree_common.c | 8 } Indirect; typedef
12 static inline void add_chain(Indirect *p, struct buffer_head *bh, block_t *v) in add_chain()
18 static inline int verify_chain(Indirect *from, Indirect *to) in verify_chain()
30 static inline Indirect *get_branch(struct inode *inode, in get_branch()
33 Indirect chain[DEPTH], in get_branch()
37 Indirect *p = chain; in get_branch()
73 Indirect *branch) in alloc_branch()
116 Indirect chain[DEPTH], in splice_branch()
117 Indirect *where, in splice_branch()
136 /* had we spliced it onto indirect block? */ in splice_branch()
[all …]
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | spectre.rst | 62 execution of indirect branches to leak privileged memory.
93 execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
95 indirect branches can be influenced by an attacker, causing gadget code
102 In Spectre variant 2 attacks, the attacker can steer speculative indirect
104 buffer of a CPU used for predicting indirect branch addresses. Such
105 poisoning could be done by indirect branching into existing code,
106 with the address offset of the indirect branch under the attacker's
109 this could cause privileged code's indirect branch to jump to a gadget
130 steer its indirect branch speculations to gadget code, and measure the
135 Branch History Buffer (BHB) to speculatively steer an indirect branch
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| H A D | indirect-target-selection.rst | 3 Indirect Target Selection (ITS)
8 of indirect branches and RETs located in the lower half of a cacheline.
14 - **eIBRS Guest/Host Isolation**: Indirect branches in KVM/kernel may still be
20 - **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
57 As only the indirect branches and RETs that have their last byte of instruction
59 the mitigation is to not allow indirect branches in the lower half.
63 added ITS-safe thunks. These safe thunks consists of indirect branch in the
66 indirect branch.
75 Note, for simplicity, indirect branches in eBPF programs are always replaced
82 thunks. But, RETs significantly outnumber indirect branches, and any benefit
[all …]
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| /linux/sound/mips/ |
| H A D | hal2.h | 13 /* Indirect status register */
28 /* Indirect address register */
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
44 /* blockin which the indirect */
71 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
72 * Indirect Data registers. Write the address to the Indirect Address register
78 * When we write to indirect registers which are larger than one word (16 bit)
79 * we have to fill more than one indirect register before writing. When we read
[all …]
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| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_adminq_cmd.h | 218 /* command structures and indirect data structures */
222 * - _data for indirect sent data
223 * - _resp for indirect return data (data which is both will use _data)
286 /* Set ARP Proxy command / response (indirect 0x0104) */
298 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
325 /* Manage MAC Address Read Command (indirect 0x0107) */
405 /* Used by many indirect commands that only pass an seid and a buffer in the
417 /* Get Switch Configuration command (indirect 0x0200)
442 /* Get Switch Configuration (indirect 0x0200)
475 /* Get Switch Resource Allocation (indirect 0x0204) */
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v4_0_5.c | 467 * @indirect: indirectly write sram
472 bool indirect) in vcn_v4_0_5_mc_resume_dpg_mode() argument
484 if (!indirect) { in vcn_v4_0_5_mc_resume_dpg_mode()
488 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
492 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
494 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
497 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
499 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
501 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
507 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
[all …]
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| H A D | vcn_v4_0_3.c | 99 int inst_idx, bool indirect);
527 * @indirect: indirectly write sram
532 bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
544 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
548 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
552 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
554 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
557 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
559 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
561 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
[all …]
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| H A D | vcn_v5_0_0.c | 434 * @indirect: indirectly write sram
439 bool indirect) in vcn_v5_0_0_mc_resume_dpg_mode() argument
451 if (!indirect) { in vcn_v5_0_0_mc_resume_dpg_mode()
454 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
457 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
459 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
462 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
464 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
466 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
472 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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| H A D | vcn_v5_0_1.c | 413 * @indirect: indirectly write sram
418 bool indirect) in vcn_v5_0_1_mc_resume_dpg_mode() argument
430 if (!indirect) { in vcn_v5_0_1_mc_resume_dpg_mode()
434 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
438 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
440 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
443 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
445 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
447 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
453 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
[all …]
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| H A D | vcn_v2_0.c | 448 bool indirect) in vcn_v2_0_mc_resume_dpg_mode() argument
456 if (!indirect) { in vcn_v2_0_mc_resume_dpg_mode()
459 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
464 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
467 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
469 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
471 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
477 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
480 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
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| H A D | vcn_v2_5.c | 677 bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
686 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
689 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
692 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
694 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
697 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
699 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
701 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
707 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
710 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
[all …]
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| H A D | vcn_v4_0.c | 517 * @indirect: indirectly write sram
522 bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
533 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
536 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
539 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
541 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
544 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
546 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
548 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
554 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
[all …]
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| H A D | jpeg_v5_0_0.c | 304 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
317 if (indirect) { in jpeg_engine_5_0_0_dpg_clock_gating_mode()
318 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
322 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
328 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
337 * @indirect: indirectly write sram
341 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_0_0_start_dpg_mode() argument
353 if (indirect) in jpeg_v5_0_0_start_dpg_mode()
357 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v5_0_0_start_dpg_mode()
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| /linux/arch/x86/kernel/ |
| H A D | ksysfs.c | 95 struct setup_indirect *indirect; in get_setup_data_size() local
114 indirect = (struct setup_indirect *)data->data; in get_setup_data_size()
116 if (indirect->type != SETUP_INDIRECT) in get_setup_data_size()
117 *size = indirect->len; in get_setup_data_size()
138 struct setup_indirect *indirect; in type_show() local
162 indirect = (struct setup_indirect *)data->data; in type_show()
164 ret = sprintf(buf, "0x%x\n", indirect->type); in type_show()
179 struct setup_indirect *indirect; in setup_data_data_read() local
203 indirect = (struct setup_indirect *)data->data; in setup_data_data_read()
205 if (indirect->type != SETUP_INDIRECT) { in setup_data_data_read()
[all …]
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| H A D | kdebugfs.c | 49 /* Is it direct data or invalid indirect one? */ in setup_data_read()
91 struct setup_indirect *indirect; in create_setup_data_nodes() local
129 indirect = (struct setup_indirect *)data->data; in create_setup_data_nodes()
131 if (indirect->type != SETUP_INDIRECT) { in create_setup_data_nodes()
132 node->paddr = indirect->addr; in create_setup_data_nodes()
133 node->type = indirect->type; in create_setup_data_nodes()
134 node->len = indirect->len; in create_setup_data_nodes()
|
| /linux/arch/m68k/math-emu/ |
| H A D | fp_decode.h | 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * a0 - will point to source/dest operand for any indirect mode
121 | .long "addr register indirect"
122 | .long "addr register indirect postincrement"
123 | .long "addr register indirect predecrement"
184 | .long "no memory indirect action/reserved","null outer displacement"
196 | test if %pc is the base register for the indirect addr mode
220 | addressing mode: address register indirect
244 | addressing mode: address register indirect with postincrement
263 | addressing mode: address register indirect with predecrement
[all …]
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| /linux/fs/ext2/ |
| H A D | inode.c | 118 } Indirect; typedef
120 static inline void add_chain(Indirect *p, struct buffer_head *bh, __le32 *v) in add_chain()
126 static inline int verify_chain(Indirect *from, Indirect *to) in verify_chain()
139 * followed (on disk) by an indirect block.
142 * data blocks at leaves and indirect blocks in intermediate nodes.
149 * we need to know is the capacity of indirect blocks (taken from the
155 * indirect block) is spelled differently, because otherwise on an
206 * ext2_get_branch - read the chain of indirect blocks leading to data
209 * @offsets: offsets of pointers in inode/indirect blocks
219 * for i>0) and chain[i].bh points to the buffer_head of i-th indirect
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| /linux/drivers/ras/amd/atl/ |
| H A D | access.c | 5 * access.c : DF Indirect Access functions
15 /* Protect the PCI config register pairs used for DF indirect access. */
19 * Data Fabric Indirect Access uses FICAA/FICAD.
21 * Fabric Indirect Configuration Access Address (FICAA): constructed based
25 * Fabric Indirect Configuration Access Data (FICAD): there are FICAD
111 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); in __df_indirect_read()
117 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); in __df_indirect_read()
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| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 8 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
17 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
27 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
37 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
42 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
47 …indirect CALL branch instructions retired. Branch prediction predicts the branch target and enabl…
57 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
62 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct…
67 …indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the b…
77 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/ |
| H A D | retired.json | 48 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
60 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
64 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
76 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
80 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
88 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | branch.json | 10 …"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a pr…
55 …"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each…
60 "BriefDescription": "Retired indirect branch instructions."
75 "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/ |
| H A D | retired.json | 40 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
52 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
56 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
68 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
72 …"PublicDescription": "Counts architecturally executed indirect branches excluding procedure return…
96 …"PublicDescription": "Counts architecturally executed indirect branches including procedure return…
|