amd/amdgpu/vcn_v5_0_0.c

434  * @indirect: indirectly write sram
439 					  bool indirect)
451 		if (!indirect) {
454 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
457 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
459 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
462 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
464 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
466 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
472 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
475 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
479 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
482 	if (!indirect)
484 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
487 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
490 	if (!indirect) {
493 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
496 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
498 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
501 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
503 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
505 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
508 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
513 		lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
516 		upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
518 		VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
520 		VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
525 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
528 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
530 		VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
533 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);
538 		adev->gfx.config.gb_addr_config, 0, indirect);
676  * @indirect: indirectly write sram
682 						     uint8_t indirect)
704  * @indirect: indirectly write sram
709 				     bool indirect)
727 	if (indirect)
734 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
738 		VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
750 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
752 	vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect);
757 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
762 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
767 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
769 	if (indirect)