amd/amdgpu/vcn_v5_0_1.c

413  * @indirect: indirectly write sram
418 					  bool indirect)
430 		if (!indirect) {
434 				 inst_idx].tmr_mc_addr_lo), 0, indirect);
438 				 inst_idx].tmr_mc_addr_hi), 0, indirect);
440 				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
443 				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
445 				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
447 				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
453 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
456 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
460 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
463 	if (!indirect)
465 			VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
468 			VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
471 	if (!indirect) {
474 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
477 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
479 			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
482 			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
484 			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
486 			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
489 			VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
495 			AMDGPU_VCN_STACK_SIZE), 0, indirect);
499 			AMDGPU_VCN_STACK_SIZE), 0, indirect);
501 		VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
503 		VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
508 		lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
511 		upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
513 		VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
516 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect);
520 		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
595  * @indirect: indirectly write sram
600 				     bool indirect)
622 	if (indirect) {
634 		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
638 		VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
650 		VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
652 	vcn_v5_0_1_mc_resume_dpg_mode(vinst, indirect);
657 		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
662 		VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
667 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
669 	if (indirect)