amd/amdgpu/jpeg_v5_0_0.c

304 	       int inst_idx, uint8_t indirect)
317 	if (indirect) {
318 		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
322 		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
324 		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
328 		WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
337  * @indirect: indirectly write sram
341 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
353 	if (indirect)
357 	jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);
360 	if (indirect)
362 			adev->gfx.config.gb_addr_config, indirect);
368 	if (indirect)
370 			JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);
375 	if (indirect) {
377 		ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);