amd/amdgpu/vcn_v4_0_3.c

99 				  int inst_idx, bool indirect);
527  * @indirect: indirectly write sram
532 					  bool indirect)
544 		if (!indirect) {
548 					inst_idx].tmr_mc_addr_lo), 0, indirect);
552 					inst_idx].tmr_mc_addr_hi), 0, indirect);
554 				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
557 				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
559 				VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
561 				VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
567 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
570 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
574 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
577 	if (!indirect)
579 			VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
582 			VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
585 	if (!indirect) {
588 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
591 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
593 			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
596 			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
598 			VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
600 			VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
603 			VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
609 				AMDGPU_VCN_STACK_SIZE), 0, indirect);
613 				AMDGPU_VCN_STACK_SIZE), 0, indirect);
615 			VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
617 			VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
622 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
625 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
627 			VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
630 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
634 		VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
636 		VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
738  * @indirect: indirectly write sram
744 						     uint8_t indirect)
771 		VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
775 		VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect);
779 		VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
783 		VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
842  * @indirect: indirectly write sram
847 				     bool indirect)
867 	if (indirect) {
878 	vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect);
886 		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
890 		VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
902 		VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
906 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
913 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
920 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
926 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
928 	vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect);
933 		VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
938 		VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
940 	vcn_v4_0_3_enable_ras(adev, inst_idx, indirect);
945 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
947 	if (indirect)
2166 				  int inst_idx, bool indirect)
2179 			      tmp, 0, indirect);
2184 			      tmp, 0, indirect);
2189 			      tmp, 0, indirect);