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/qemu/target/sparc/
H A Dint32_helper.c39 [TT_EXTINT | 0x1] = "External Interrupt 1",
40 [TT_EXTINT | 0x2] = "External Interrupt 2",
41 [TT_EXTINT | 0x3] = "External Interrupt 3",
42 [TT_EXTINT | 0x4] = "External Interrupt 4",
43 [TT_EXTINT | 0x5] = "External Interrupt 5",
44 [TT_EXTINT | 0x6] = "External Interrupt 6",
45 [TT_EXTINT | 0x7] = "External Interrupt 7",
46 [TT_EXTINT | 0x8] = "External Interrupt 8",
47 [TT_EXTINT | 0x9] = "External Interrupt 9",
48 [TT_EXTINT | 0xa] = "External Interrupt 10",
[all …]
H A Dint64_helper.c47 [TT_EXTINT | 0x1] = "External Interrupt 1",
48 [TT_EXTINT | 0x2] = "External Interrupt 2",
49 [TT_EXTINT | 0x3] = "External Interrupt 3",
50 [TT_EXTINT | 0x4] = "External Interrupt 4",
51 [TT_EXTINT | 0x5] = "External Interrupt 5",
52 [TT_EXTINT | 0x6] = "External Interrupt 6",
53 [TT_EXTINT | 0x7] = "External Interrupt 7",
54 [TT_EXTINT | 0x8] = "External Interrupt 8",
55 [TT_EXTINT | 0x9] = "External Interrupt 9",
56 [TT_EXTINT | 0xa] = "External Interrupt 10",
[all …]
H A Dasi.h61 /* These ASI flushes affect external caches too. */
248 #define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
249 #define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
256 #define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
257 #define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
258 #define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
259 #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
/qemu/tests/qemu-iotests/
H A D082.out56 data_file=<str> - File name of an external data file
57 data_file_raw=<bool (on/off)> - The external data file must stay valid as a raw image
82 data_file=<str> - File name of an external data file
83 data_file_raw=<bool (on/off)> - The external data file must stay valid as a raw image
108 data_file=<str> - File name of an external data file
109 data_file_raw=<bool (on/off)> - The external data file must stay valid as a raw image
134 data_file=<str> - File name of an external data file
135 data_file_raw=<bool (on/off)> - The external data file must stay valid as a raw image
160 data_file=<str> - File name of an external data file
161 data_file_raw=<bool (on/off)> - The external data file must stay valid as a raw image
[all …]
H A D243.out27 === External data file: preallocation=off ===
35 === External data file: preallocation=metadata ===
43 === External data file: preallocation=falloc ===
51 === External data file: preallocation=full ===
H A D2444 # Test qcow2 with external data files
46 # External data files do not work with compat=0.10, and because we use
47 # our own external data file, we cannot let the user specify one
51 echo "=== Create and open image with external data file ==="
109 echo "=== Standalone image with external data file (efficient) ==="
144 # stale data in the external data file
158 echo "=== Standalone image with external data file (valid raw) ==="
185 # they can contain stale data in the external data file. Instead, zero
186 # clusters must be zeroed in the external data file too.
H A D28945 # there is an external data file or not; so we create one exactly when
50 echo === Avoid freeing external data clusters on failure ===
60 # Test what happens when there is an error when writing to an external
H A D24344 # External data files do not work with compat=0.10, and because there
45 # is an explicit case for external data files here, we cannot allow
69 echo "=== External data file: preallocation=$mode ==="
H A D29245 # but with an external data file, it will show that instead of the
46 # file we want to check. So just skip this test for external data
/qemu/hw/intc/
H A Dexynos4210_combiner.c74 VMSTATE_UINT32(external, Exynos4210CombinerState),
140 DPRINTF("%s raise IRQ[%d]\n", s->external ? "EXT" : "INT", group_n); in exynos4210_combiner_update()
156 DPRINTF("%s lower IRQ[%d]\n", s->external ? "EXT" : "INT", group_n); in exynos4210_combiner_update()
210 s->external ? "EXT" : "INT", in exynos4210_combiner_write()
230 s->external ? "EXT" : "INT", in exynos4210_combiner_write()
261 /* Process a change in an external IRQ input. */
270 if (s->external && group_n >= EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ) { in exynos4210_combiner_handler()
271 DPRINTF("%s unallowed IRQ group 0x%x\n", s->external ? "EXT" : "INT" in exynos4210_combiner_handler()
329 DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0),
/qemu/hw/sh4/
H A Dsh7750_regs.h236 #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */
237 #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */
238 #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */
239 #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */
240 #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */
241 #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */
242 #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */
243 #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */
244 #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */
245 #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */
[all …]
/qemu/hw/arm/
H A Dexynos4210.c55 /* Interrupt Group of External Interrupt Combiner for I2C */
68 /* Interrupt Group of External Interrupt Combiner for UART */
71 /* External GIC */
193 * External GIC sources which are not from External Interrupt Combiner or
194 * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
333 * These IRQs contain split Int/External Combiner and External Gic IRQs.
349 /* MCT_G0 is passed to External GIC */ in exynos4210_init_board_irqs()
353 /* MCT_G1 is passed to External and GIC */ in exynos4210_init_board_irqs()
367 * and possibly also to the external GIC. in exynos4210_init_board_irqs()
404 /* these IDs are passed to Internal Combiner and External GIC */ in exynos4210_init_board_irqs()
[all …]
/qemu/tests/qemu-iotests/tests/
H A Dmirror-sparse74 if test $creation = external; then
113 do_test external ignore off sparse
114 do_test external unmap off sparse
115 do_test external unmap unmap sparse
/qemu/include/hw/arm/
H A Darmv7m.h40 * + Unnamed GPIO input lines: external IRQ lines for the NVIC
45 * + Property "num-irq": number of external IRQ lines
62 * + Clock input "refclk" is the external reference clock for the systick timers
H A Dexynos4210.h63 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
77 * We need one splitter for every external combiner input, plus
79 * minus one for every external combiner ID in second or later
/qemu/docs/devel/
H A Dreplay.rst16 non-deterministic events including external input, hardware clocks,
21 Devices' models that have non-deterministic input from external devices were
22 changed to write every external event into the execution log immediately.
47 * recording of random numbers obtained from the external sources
53 designed to allow deterministic execution in absence of external inputs
153 speed, use virtual clock with EXTERNAL attribute. It is not deterministic,
/qemu/docs/interop/
H A Dqcow2.rst30 Note: backing files are incompatible with raw external data
109 Bit 2: External data file bit. If this bit is set, an
110 external data file is used. Guest clusters are
111 then stored in the external data file. For such
112 images, clusters in the external data file are
118 An External Data File Name header extension may
160 Bit 1: Raw external data bit
161 If this bit is set, the external data file can
171 This bit may only be set if the External Data
261 0x44415441 - External data file name string
[all …]
/qemu/include/hw/intc/
H A Dexynos4210_combiner.h52 uint32_t external; /* 1 means that this combiner is external */ member
/qemu/hw/gpio/
H A Dpcf8574.c44 uint8_t input; /* external electrical line state */
47 qemu_irq intrq; /* External irq request */
60 /* we driving line low or external circuit does that */ in pcf8574_line_state()
/qemu/include/exec/
H A Dcpu-interrupt.h18 * External hardware interrupt pending.
39 * Several target-specific external hardware interrupts. Each target/cpu.h
/qemu/hw/sensor/
H A Dmax34451.c95 | | optionally margined by OUT0 of external DS4424 at I2C address A0h.|
98 | | optionally margined by OUT1 of external DS4424 at I2C address A0h.|
101 | | optionally margined by OUT2 of external DS4424 at I2C address A0h.|
104 | | optionally margined by OUT3 of external DS4424 at I2C address A0h.|
116 | 17 | External DS75LV temperature sensor with I2C address 90h. |
118 | 18 | External DS75LV temperature sensor with I2C address 92h. |
120 | 19 | External DS75LV temperature sensor with I2C address 94h. |
122 | 20 | External DS75LV temperature sensor with I2C address 96h. |
/qemu/include/system/
H A Dspdm-socket.h27 * spdm_socket_connect: connect to an external SPDM socket
31 * This will connect to an external SPDM socket server. On error
/qemu/include/hw/acpi/
H A Dghes.h34 /* External Interrupt */
52 /* External Interrupt - GSIV, ACPI 6.1: 18.3.2.9, Table 18-345 */
/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h189 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
237 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
290 * External interrupt vectors/levels.
293 * map to external BInterrupt<n> pins, for those interrupts
294 * configured as external (level-triggered, edge-triggered, or NMI).
298 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
328 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h185 #define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
228 #define XCHAL_HAVE_DEBUG_EXTERN_INT 0 /* OCD external db interrupt */
269 * External interrupt vectors/levels.
272 * map to external BInterrupt<n> pins, for those interrupts
273 * configured as external (level-triggered, edge-triggered, or NMI).
277 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
300 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */

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