1*b9e3bf88SRichard Henderson /* 2*b9e3bf88SRichard Henderson * Flags for use with cpu_interrupt() 3*b9e3bf88SRichard Henderson * 4*b9e3bf88SRichard Henderson * Copyright (c) 2003 Fabrice Bellard 5*b9e3bf88SRichard Henderson * SPDX-License-Identifier: LGPL-2.1-or-later 6*b9e3bf88SRichard Henderson */ 7*b9e3bf88SRichard Henderson 8*b9e3bf88SRichard Henderson #ifndef CPU_INTERRUPT_H 9*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_H 10*b9e3bf88SRichard Henderson 11*b9e3bf88SRichard Henderson /* 12*b9e3bf88SRichard Henderson * The numbers assigned here are non-sequential in order to preserve binary 13*b9e3bf88SRichard Henderson * compatibility with the vmstate dump. Bit 0 (0x0001) was previously used 14*b9e3bf88SRichard Henderson * for CPU_INTERRUPT_EXIT, and is cleared when loading the vmstate dump. 15*b9e3bf88SRichard Henderson */ 16*b9e3bf88SRichard Henderson 17*b9e3bf88SRichard Henderson /* 18*b9e3bf88SRichard Henderson * External hardware interrupt pending. 19*b9e3bf88SRichard Henderson * This is typically used for interrupts from devices. 20*b9e3bf88SRichard Henderson */ 21*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_HARD 0x0002 22*b9e3bf88SRichard Henderson 23*b9e3bf88SRichard Henderson /* 24*b9e3bf88SRichard Henderson * Exit the current TB. This is typically used when some system-level device 25*b9e3bf88SRichard Henderson * makes some change to the memory mapping. E.g. the a20 line change. 26*b9e3bf88SRichard Henderson */ 27*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_EXITTB 0x0004 28*b9e3bf88SRichard Henderson 29*b9e3bf88SRichard Henderson /* Halt the CPU. */ 30*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_HALT 0x0020 31*b9e3bf88SRichard Henderson 32*b9e3bf88SRichard Henderson /* Debug event pending. */ 33*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_DEBUG 0x0080 34*b9e3bf88SRichard Henderson 35*b9e3bf88SRichard Henderson /* Reset signal. */ 36*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_RESET 0x0400 37*b9e3bf88SRichard Henderson 38*b9e3bf88SRichard Henderson /* 39*b9e3bf88SRichard Henderson * Several target-specific external hardware interrupts. Each target/cpu.h 40*b9e3bf88SRichard Henderson * should define proper names based on these defines. 41*b9e3bf88SRichard Henderson */ 42*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_EXT_0 0x0008 43*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_EXT_1 0x0010 44*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_EXT_2 0x0040 45*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_EXT_3 0x0200 46*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_EXT_4 0x1000 47*b9e3bf88SRichard Henderson 48*b9e3bf88SRichard Henderson /* 49*b9e3bf88SRichard Henderson * Several target-specific internal interrupts. These differ from the 50*b9e3bf88SRichard Henderson * preceding target-specific interrupts in that they are intended to 51*b9e3bf88SRichard Henderson * originate from within the cpu itself, typically in response to some 52*b9e3bf88SRichard Henderson * instruction being executed. These, therefore, are not masked while 53*b9e3bf88SRichard Henderson * single-stepping within the debugger. 54*b9e3bf88SRichard Henderson */ 55*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_INT_0 0x0100 56*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_INT_1 0x0800 57*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_TGT_INT_2 0x2000 58*b9e3bf88SRichard Henderson 59*b9e3bf88SRichard Henderson /* First unused bit: 0x4000. */ 60*b9e3bf88SRichard Henderson 61*b9e3bf88SRichard Henderson /* The set of all bits that should be masked when single-stepping. */ 62*b9e3bf88SRichard Henderson #define CPU_INTERRUPT_SSTEP_MASK \ 63*b9e3bf88SRichard Henderson (CPU_INTERRUPT_HARD \ 64*b9e3bf88SRichard Henderson | CPU_INTERRUPT_TGT_EXT_0 \ 65*b9e3bf88SRichard Henderson | CPU_INTERRUPT_TGT_EXT_1 \ 66*b9e3bf88SRichard Henderson | CPU_INTERRUPT_TGT_EXT_2 \ 67*b9e3bf88SRichard Henderson | CPU_INTERRUPT_TGT_EXT_3 \ 68*b9e3bf88SRichard Henderson | CPU_INTERRUPT_TGT_EXT_4) 69*b9e3bf88SRichard Henderson 70*b9e3bf88SRichard Henderson #endif /* CPU_INTERRUPT_H */ 71