1a8b991b5SMarkus Armbruster #ifndef SPARC_ASI_H 2a8b991b5SMarkus Armbruster #define SPARC_ASI_H 368a03b8cSRichard Henderson 468a03b8cSRichard Henderson /* asi.h: Address Space Identifier values for the sparc. 568a03b8cSRichard Henderson * 668a03b8cSRichard Henderson * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) 768a03b8cSRichard Henderson * 868a03b8cSRichard Henderson * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au) 968a03b8cSRichard Henderson * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su> 1068a03b8cSRichard Henderson */ 1168a03b8cSRichard Henderson 1268a03b8cSRichard Henderson /* The first batch are for the sun4c. */ 1368a03b8cSRichard Henderson 1468a03b8cSRichard Henderson #define ASI_NULL1 0x00 1568a03b8cSRichard Henderson #define ASI_NULL2 0x01 1668a03b8cSRichard Henderson 1768a03b8cSRichard Henderson /* sun4c and sun4 control registers and mmu/vac ops */ 1868a03b8cSRichard Henderson #define ASI_CONTROL 0x02 1968a03b8cSRichard Henderson #define ASI_SEGMAP 0x03 2068a03b8cSRichard Henderson #define ASI_PTE 0x04 2168a03b8cSRichard Henderson #define ASI_HWFLUSHSEG 0x05 2268a03b8cSRichard Henderson #define ASI_HWFLUSHPAGE 0x06 2368a03b8cSRichard Henderson #define ASI_REGMAP 0x06 2468a03b8cSRichard Henderson #define ASI_HWFLUSHCONTEXT 0x07 2568a03b8cSRichard Henderson 2668a03b8cSRichard Henderson #define ASI_USERTXT 0x08 2768a03b8cSRichard Henderson #define ASI_KERNELTXT 0x09 2868a03b8cSRichard Henderson #define ASI_USERDATA 0x0a 2968a03b8cSRichard Henderson #define ASI_KERNELDATA 0x0b 3068a03b8cSRichard Henderson 3168a03b8cSRichard Henderson /* VAC Cache flushing on sun4c and sun4 */ 3268a03b8cSRichard Henderson #define ASI_FLUSHSEG 0x0c 3368a03b8cSRichard Henderson #define ASI_FLUSHPG 0x0d 3468a03b8cSRichard Henderson #define ASI_FLUSHCTX 0x0e 3568a03b8cSRichard Henderson 3668a03b8cSRichard Henderson /* SPARCstation-5: only 6 bits are decoded. */ 3768a03b8cSRichard Henderson /* wo = Write Only, rw = Read Write; */ 3868a03b8cSRichard Henderson /* ss = Single Size, as = All Sizes; */ 3968a03b8cSRichard Henderson #define ASI_M_RES00 0x00 /* Don't touch... */ 4068a03b8cSRichard Henderson #define ASI_M_UNA01 0x01 /* Same here... */ 4168a03b8cSRichard Henderson #define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */ 4268a03b8cSRichard Henderson #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */ 4368a03b8cSRichard Henderson #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */ 4468a03b8cSRichard Henderson #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */ 4568a03b8cSRichard Henderson #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */ 4668a03b8cSRichard Henderson #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */ 4768a03b8cSRichard Henderson #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */ 4868a03b8cSRichard Henderson #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */ 4968a03b8cSRichard Henderson #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */ 5068a03b8cSRichard Henderson #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */ 5168a03b8cSRichard Henderson #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */ 5268a03b8cSRichard Henderson #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */ 5368a03b8cSRichard Henderson #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */ 5468a03b8cSRichard Henderson #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */ 5568a03b8cSRichard Henderson 5668a03b8cSRichard Henderson /* The following cache flushing ASIs work only with the 'sta' 5768a03b8cSRichard Henderson * instruction. Results are unpredictable for 'swap' and 'ldstuba', 5868a03b8cSRichard Henderson * so don't do it. 5968a03b8cSRichard Henderson */ 6068a03b8cSRichard Henderson 6168a03b8cSRichard Henderson /* These ASI flushes affect external caches too. */ 6268a03b8cSRichard Henderson #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */ 6368a03b8cSRichard Henderson #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */ 6468a03b8cSRichard Henderson #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */ 6568a03b8cSRichard Henderson #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */ 6668a03b8cSRichard Henderson #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */ 6768a03b8cSRichard Henderson 6868a03b8cSRichard Henderson /* Block-copy operations are available only on certain V8 cpus. */ 6968a03b8cSRichard Henderson #define ASI_M_BCOPY 0x17 /* Block copy */ 7068a03b8cSRichard Henderson 7168a03b8cSRichard Henderson /* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */ 7268a03b8cSRichard Henderson #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */ 7368a03b8cSRichard Henderson #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */ 7468a03b8cSRichard Henderson #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */ 7568a03b8cSRichard Henderson #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */ 7668a03b8cSRichard Henderson #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */ 7768a03b8cSRichard Henderson 7868a03b8cSRichard Henderson /* Block-fill operations are available on certain V8 cpus */ 7968a03b8cSRichard Henderson #define ASI_M_BFILL 0x1F 8068a03b8cSRichard Henderson 8168a03b8cSRichard Henderson /* This allows direct access to main memory, actually 0x20 to 0x2f are 8268a03b8cSRichard Henderson * the available ASI's for physical ram pass-through, but I don't have 8368a03b8cSRichard Henderson * any idea what the other ones do.... 8468a03b8cSRichard Henderson */ 8568a03b8cSRichard Henderson 8668a03b8cSRichard Henderson #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */ 8768a03b8cSRichard Henderson #define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */ 8868a03b8cSRichard Henderson #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */ 8968a03b8cSRichard Henderson #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */ 9068a03b8cSRichard Henderson #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */ 9168a03b8cSRichard Henderson #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */ 9268a03b8cSRichard Henderson #define ASI_M_SBUS 0x2E /* Direct SBus access */ 9368a03b8cSRichard Henderson #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */ 9468a03b8cSRichard Henderson 9568a03b8cSRichard Henderson 9668a03b8cSRichard Henderson /* This is ROSS HyperSparc only. */ 9768a03b8cSRichard Henderson #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */ 9868a03b8cSRichard Henderson 9968a03b8cSRichard Henderson /* Tsunami/Viking/TurboSparc i/d cache flash clear. */ 10068a03b8cSRichard Henderson #define ASI_M_IC_FLCLEAR 0x36 10168a03b8cSRichard Henderson #define ASI_M_DC_FLCLEAR 0x37 10268a03b8cSRichard Henderson 10368a03b8cSRichard Henderson #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */ 10468a03b8cSRichard Henderson 10568a03b8cSRichard Henderson #define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */ 10668a03b8cSRichard Henderson /* only available on SuperSparc I */ 10768a03b8cSRichard Henderson /* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking */ 10868a03b8cSRichard Henderson 10968a03b8cSRichard Henderson #define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */ 11068a03b8cSRichard Henderson 11168a03b8cSRichard Henderson /* LEON ASI */ 11268a03b8cSRichard Henderson #define ASI_LEON_NOCACHE 0x01 11368a03b8cSRichard Henderson 11468a03b8cSRichard Henderson #define ASI_LEON_DCACHE_MISS 0x01 11568a03b8cSRichard Henderson 11668a03b8cSRichard Henderson #define ASI_LEON_CACHEREGS 0x02 11768a03b8cSRichard Henderson #define ASI_LEON_IFLUSH 0x10 11868a03b8cSRichard Henderson #define ASI_LEON_DFLUSH 0x11 11968a03b8cSRichard Henderson 12068a03b8cSRichard Henderson #define ASI_LEON_MMUFLUSH 0x18 12168a03b8cSRichard Henderson #define ASI_LEON_MMUREGS 0x19 12268a03b8cSRichard Henderson #define ASI_LEON_BYPASS 0x1c 12368a03b8cSRichard Henderson #define ASI_LEON_FLUSH_PAGE 0x10 12468a03b8cSRichard Henderson 12568a03b8cSRichard Henderson /* V9 Architecture mandary ASIs. */ 12668a03b8cSRichard Henderson #define ASI_N 0x04 /* Nucleus */ 12768a03b8cSRichard Henderson #define ASI_NL 0x0c /* Nucleus, little endian */ 12868a03b8cSRichard Henderson #define ASI_AIUP 0x10 /* Primary, user */ 12968a03b8cSRichard Henderson #define ASI_AIUS 0x11 /* Secondary, user */ 13068a03b8cSRichard Henderson #define ASI_AIUPL 0x18 /* Primary, user, little endian */ 13168a03b8cSRichard Henderson #define ASI_AIUSL 0x19 /* Secondary, user, little endian */ 13268a03b8cSRichard Henderson #define ASI_P 0x80 /* Primary, implicit */ 13368a03b8cSRichard Henderson #define ASI_S 0x81 /* Secondary, implicit */ 13468a03b8cSRichard Henderson #define ASI_PNF 0x82 /* Primary, no fault */ 13568a03b8cSRichard Henderson #define ASI_SNF 0x83 /* Secondary, no fault */ 13668a03b8cSRichard Henderson #define ASI_PL 0x88 /* Primary, implicit, l-endian */ 13768a03b8cSRichard Henderson #define ASI_SL 0x89 /* Secondary, implicit, l-endian */ 13868a03b8cSRichard Henderson #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ 13968a03b8cSRichard Henderson #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ 14068a03b8cSRichard Henderson 14168a03b8cSRichard Henderson /* SpitFire and later extended ASIs. The "(III)" marker designates 14268a03b8cSRichard Henderson * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates 14368a03b8cSRichard Henderson * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific 14468a03b8cSRichard Henderson * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4 14568a03b8cSRichard Henderson * and later ASIs. 14668a03b8cSRichard Henderson */ 147*eeb3f592SRichard Henderson #define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */ 148*eeb3f592SRichard Henderson #define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */ 1498b81968cSMichael Tokarev #define ASI_REAL 0x14 /* Real address, cacheable */ 150690f50c2SManos Pitsidianakis #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */ 151690f50c2SManos Pitsidianakis #define ASI_REAL_IO 0x15 /* Real address, non-cacheable */ 15268a03b8cSRichard Henderson #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ 15368a03b8cSRichard Henderson #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ 15468a03b8cSRichard Henderson #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ 1558b81968cSMichael Tokarev #define ASI_REAL_L 0x1c /* Real address, cacheable, LE */ 156690f50c2SManos Pitsidianakis #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/ 157690f50c2SManos Pitsidianakis #define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */ 15868a03b8cSRichard Henderson #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ 15968a03b8cSRichard Henderson #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ 16068a03b8cSRichard Henderson #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ 16168a03b8cSRichard Henderson #define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ 16268a03b8cSRichard Henderson #define ASI_MMU 0x21 /* (4V) MMU Context Registers */ 1631d854963SRichard Henderson #define ASI_TWINX_AIUP 0x22 /* twin load, primary user */ 1641d854963SRichard Henderson #define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */ 16568a03b8cSRichard Henderson #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, 16668a03b8cSRichard Henderson * secondary, user 16768a03b8cSRichard Henderson */ 1688b81968cSMichael Tokarev #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */ 16968a03b8cSRichard Henderson #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ 1708b81968cSMichael Tokarev #define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */ 17168a03b8cSRichard Henderson #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ 1721d854963SRichard Henderson #define ASI_TWINX_N 0x27 /* twin load, nucleus */ 1731d854963SRichard Henderson #define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */ 1741d854963SRichard Henderson #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */ 1758b81968cSMichael Tokarev #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */ 1768b81968cSMichael Tokarev #define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */ 17768a03b8cSRichard Henderson #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ 1781d854963SRichard Henderson #define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */ 17968a03b8cSRichard Henderson #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ 18068a03b8cSRichard Henderson #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ 18168a03b8cSRichard Henderson #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ 18268a03b8cSRichard Henderson #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ 18368a03b8cSRichard Henderson #define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ 18468a03b8cSRichard Henderson #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ 18568a03b8cSRichard Henderson #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ 18668a03b8cSRichard Henderson #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ 18768a03b8cSRichard Henderson #define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ 18868a03b8cSRichard Henderson #define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ 18968a03b8cSRichard Henderson #define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ 19068a03b8cSRichard Henderson #define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ 19168a03b8cSRichard Henderson #define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ 19268a03b8cSRichard Henderson #define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ 19368a03b8cSRichard Henderson #define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ 19468a03b8cSRichard Henderson #define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ 19568a03b8cSRichard Henderson #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ 19668a03b8cSRichard Henderson #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ 19768a03b8cSRichard Henderson #define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ 19868a03b8cSRichard Henderson #define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ 19968a03b8cSRichard Henderson #define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ 20068a03b8cSRichard Henderson #define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ 20168a03b8cSRichard Henderson #define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ 20268a03b8cSRichard Henderson #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ 20368a03b8cSRichard Henderson #define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ 20468a03b8cSRichard Henderson #define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ 20568a03b8cSRichard Henderson #define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ 20668a03b8cSRichard Henderson #define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ 20768a03b8cSRichard Henderson #define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ 20868a03b8cSRichard Henderson #define ASI_UPA_CONFIG 0x4a /* UPA config space */ 20968a03b8cSRichard Henderson #define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ 21068a03b8cSRichard Henderson #define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ 21168a03b8cSRichard Henderson #define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ 21268a03b8cSRichard Henderson #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ 21368a03b8cSRichard Henderson #define ASI_AFSR 0x4c /* Async fault status register */ 21468a03b8cSRichard Henderson #define ASI_AFAR 0x4d /* Async fault address register */ 21568a03b8cSRichard Henderson #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ 2164ec3e346SArtyom Tarasenko #define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */ 21768a03b8cSRichard Henderson #define ASI_IMMU 0x50 /* Insn-MMU main register space */ 21868a03b8cSRichard Henderson #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ 21968a03b8cSRichard Henderson #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ 22068a03b8cSRichard Henderson #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ 22168a03b8cSRichard Henderson #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ 22268a03b8cSRichard Henderson #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ 22368a03b8cSRichard Henderson #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ 22468a03b8cSRichard Henderson #define ASI_DMMU 0x58 /* Data-MMU main register space */ 22568a03b8cSRichard Henderson #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ 22668a03b8cSRichard Henderson #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ 22768a03b8cSRichard Henderson #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ 22868a03b8cSRichard Henderson #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ 22968a03b8cSRichard Henderson #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ 23068a03b8cSRichard Henderson #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ 23168a03b8cSRichard Henderson #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ 23268a03b8cSRichard Henderson #define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ 23368a03b8cSRichard Henderson #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ 23468a03b8cSRichard Henderson #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ 23568a03b8cSRichard Henderson #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ 2368b81968cSMichael Tokarev #define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ 23768a03b8cSRichard Henderson #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ 23868a03b8cSRichard Henderson #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ 23968a03b8cSRichard Henderson #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ 24068a03b8cSRichard Henderson #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ 24168a03b8cSRichard Henderson #define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ 24268a03b8cSRichard Henderson #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ 24368a03b8cSRichard Henderson #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ 24468a03b8cSRichard Henderson #define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ 24568a03b8cSRichard Henderson #define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ 24668a03b8cSRichard Henderson #define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ 24768a03b8cSRichard Henderson #define ASI_EC_W 0x76 /* E-cache diag write access */ 24868a03b8cSRichard Henderson #define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ 24968a03b8cSRichard Henderson #define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ 25068a03b8cSRichard Henderson #define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ 25168a03b8cSRichard Henderson #define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ 25268a03b8cSRichard Henderson #define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ 25368a03b8cSRichard Henderson #define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ 25468a03b8cSRichard Henderson #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/ 25568a03b8cSRichard Henderson #define ASI_EC_R 0x7e /* E-cache diag read access */ 25668a03b8cSRichard Henderson #define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ 25768a03b8cSRichard Henderson #define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ 25868a03b8cSRichard Henderson #define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ 25968a03b8cSRichard Henderson #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ 26068a03b8cSRichard Henderson #define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ 26168a03b8cSRichard Henderson #define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ 262*eeb3f592SRichard Henderson #define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */ 263*eeb3f592SRichard Henderson #define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */ 26468a03b8cSRichard Henderson #define ASI_PIC 0xb0 /* (NG4) PIC registers */ 26568a03b8cSRichard Henderson #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ 26668a03b8cSRichard Henderson #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ 26768a03b8cSRichard Henderson #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ 26868a03b8cSRichard Henderson #define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ 26968a03b8cSRichard Henderson #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ 27068a03b8cSRichard Henderson #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ 27168a03b8cSRichard Henderson #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ 27268a03b8cSRichard Henderson #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ 27368a03b8cSRichard Henderson #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ 27468a03b8cSRichard Henderson #define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ 27568a03b8cSRichard Henderson #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ 27668a03b8cSRichard Henderson #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ 27768a03b8cSRichard Henderson #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ 27868a03b8cSRichard Henderson #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ 27968a03b8cSRichard Henderson #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ 28068a03b8cSRichard Henderson #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ 28168a03b8cSRichard Henderson #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ 28268a03b8cSRichard Henderson #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ 28368a03b8cSRichard Henderson #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ 28468a03b8cSRichard Henderson #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ 28568a03b8cSRichard Henderson #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ 28668a03b8cSRichard Henderson #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ 2871d854963SRichard Henderson #define ASI_TWINX_P 0xe2 /* twin load, primary implicit */ 28868a03b8cSRichard Henderson #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, 2891d854963SRichard Henderson * primary, implicit */ 2901d854963SRichard Henderson #define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */ 29168a03b8cSRichard Henderson #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load, 2921d854963SRichard Henderson * secondary, implicit */ 2931d854963SRichard Henderson #define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */ 2941d854963SRichard Henderson #define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE */ 29568a03b8cSRichard Henderson #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ 29668a03b8cSRichard Henderson #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ 29768a03b8cSRichard Henderson #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load, 29868a03b8cSRichard Henderson * Most-Recently-Used, primary, 29968a03b8cSRichard Henderson * implicit 30068a03b8cSRichard Henderson */ 30168a03b8cSRichard Henderson #define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load, 30268a03b8cSRichard Henderson * Most-Recently-Used, secondary, 30368a03b8cSRichard Henderson * implicit 30468a03b8cSRichard Henderson */ 30568a03b8cSRichard Henderson #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ 30668a03b8cSRichard Henderson #define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ 30768a03b8cSRichard Henderson #define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load, 30868a03b8cSRichard Henderson * Most-Recently-Used, primary, 30968a03b8cSRichard Henderson * implicit, little-endian 31068a03b8cSRichard Henderson */ 31168a03b8cSRichard Henderson #define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load, 31268a03b8cSRichard Henderson * Most-Recently-Used, secondary, 31368a03b8cSRichard Henderson * implicit, little-endian 31468a03b8cSRichard Henderson */ 31568a03b8cSRichard Henderson 316a8b991b5SMarkus Armbruster #endif /* SPARC_ASI_H */ 317