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Searched refs:spr_cb (Results 1 – 14 of 14) sorted by relevance

/qemu/target/ppc/
H A Dgdbstub.c308 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_gen_spr_feature()
309 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature()
335 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_gen_spr_feature()
336 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature()
356 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_find_spr_idx()
357 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_find_spr_idx()
H A Dppc-qmp-cmds.c158 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { in target_get_monitor_def()
159 ppc_spr_t *spr = &env->spr_cb[i]; in target_get_monitor_def()
H A Dtranslate.c200 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ member
4112 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4115 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4117 read_cb = ctx->spr_cb[sprn].hea_read; in gen_op_mfspr()
4119 read_cb = ctx->spr_cb[sprn].oea_read; in gen_op_mfspr()
4296 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4299 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4301 write_cb = ctx->spr_cb[sprn].hea_write; in gen_mtspr()
4303 write_cb = ctx->spr_cb[sprn].oea_write; in gen_mtspr()
6506 ctx->spr_cb = env->spr_cb; in ppc_tr_init_disas_context()
H A Dmachine.c232 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; in cpu_post_load()
H A Dhelper_regs.c406 ppc_spr_t *spr = &env->spr_cb[num]; in _spr_register()
H A Dcpu.h1290 ppc_spr_t spr_cb[1024]; member
2978 return cpu->env.spr_cb[spr].name != NULL; in ppc_has_spr()
H A Dkvm.c980 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_put_registers()
1280 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_get_registers()
H A Dcpu_init.c7338 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in ppc_cpu_reset_hold()
7339 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_cpu_reset_hold()
7749 if (env->spr_cb[SPR_LPCR].name) { in ppc_cpu_dump_state()
7763 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ in ppc_cpu_dump_state()
7766 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ in ppc_cpu_dump_state()
/qemu/hw/ppc/
H A Dspapr_cpu_core.c279 env->spr_cb[SPR_PIR].default_value = cs->cpu_index; in spapr_realize_vcpu()
280 env->spr_cb[SPR_TIR].default_value = thread_index; in spapr_realize_vcpu()
282 env->spr_cb[SPR_HASHPKEYR].default_value = spapr->hashpkey_val; in spapr_realize_vcpu()
H A Dpnv_core.c307 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; in pnv_core_cpu_realize()
308 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; in pnv_core_cpu_realize()
H A Dppc.c1525 return env->spr_cb[SPR_PIR].default_value; in ppc_cpu_pir()
1531 return env->spr_cb[SPR_TIR].default_value; in ppc_cpu_tir()
H A De500.c968 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; in ppce500_init()
/qemu/hw/intc/
H A Dxive2.c499 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_ctx()
578 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line()
749 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx()
H A Dxive.c1652 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive_tctx_hw_cam_line()