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Searched refs:spr (Results 1 – 25 of 47) sorted by relevance

12

/qemu/target/ppc/
H A Dpower8-pmu.c27 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; in pmc_has_overflow_enabled()
30 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; in pmc_has_overflow_enabled()
39 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in pmu_update_summaries()
40 target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1]; in pmu_update_summaries()
88 if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { in hreg_bhrb_filter_update()
94 ifm = (env->spr[SPR_POWER_MMCRA] & MMCRA_IFM_MASK) >> MMCRA_IFM_SHIFT; in hreg_bhrb_filter_update()
122 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAO) { in pmu_mmcr01a_updated()
138 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in pmu_increment_insns()
144 tmp = env->spr[SPR_POWER_PMC1]; in pmu_increment_insns()
150 env->spr[SPR_POWER_PMC1] = tmp; in pmu_increment_insns()
[all …]
H A Dmmu-booke.c83 env->spr[SPR_40x_PID], i)) { in mmu40x_get_physical_address()
87 zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3; in mmu40x_get_physical_address()
107 env->spr[SPR_40x_ESR] = 1 << 22; in mmu40x_get_physical_address()
120 env->spr[SPR_40x_ESR] = 0; in mmu40x_get_physical_address()
137 if (ppcemb_tlb_check(env, tlb, raddr, addr, env->spr[SPR_BOOKE_PID], i)) { in mmubooke_check_pid()
146 if (env->spr[SPR_BOOKE_PID1] && in mmubooke_check_pid()
147 ppcemb_tlb_check(env, tlb, raddr, addr, env->spr[SPR_BOOKE_PID1], i)) { in mmubooke_check_pid()
150 if (env->spr[SPR_BOOKE_PID2] && in mmubooke_check_pid()
151 ppcemb_tlb_check(env, tlb, raddr, addr, env->spr[SPR_BOOKE_PID2], i)) { in mmubooke_check_pid()
293 epidr = env->spr[SPR_BOOKE_EPSC]; in mmubooke206_get_as()
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H A Dtcg-excp_helper.c183 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
184 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
187 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
188 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
191 if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
206 HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
207 HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
208 HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
209 HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
226 env->spr[SPR_40x_DEAR] = vaddr; in ppc_cpu_do_unaligned_access()
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H A Dmisc_helper.c37 env->spr[sprn]); in helper_load_dump_spr()
43 env->spr[sprn]); in helper_store_dump_spr()
53 env->spr[sprn] = val; in helper_spr_core_write_generic()
59 cenv->spr[sprn] = val; in helper_spr_core_write_generic()
73 env->spr[sprn] &= ~1U; in helper_spr_write_CTRL()
74 env->spr[sprn] |= run; in helper_spr_write_CTRL()
76 ts_mask = ~(1U << (8 + env->spr[SPR_TIR])); in helper_spr_write_CTRL()
77 ts = run << (8 + env->spr[SPR_TIR]); in helper_spr_write_CTRL()
82 cenv->spr[sprn] &= ts_mask; in helper_spr_write_CTRL()
83 cenv->spr[sprn] |= ts; in helper_spr_write_CTRL()
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H A Dmmu_helper.c442 effR = FIELD_EX64(env->msr, MSR, HV) ? r : env->spr[SPR_LPCR] & LPCR_HR; in helper_tlbie_isa300()
565 RPN = env->spr[SPR_RPA]; in do_6xx_tlb()
567 CMP = env->spr[SPR_ICMP]; in do_6xx_tlb()
568 EPN = env->spr[SPR_IMISS]; in do_6xx_tlb()
570 CMP = env->spr[SPR_DCMP]; in do_6xx_tlb()
571 EPN = env->spr[SPR_DMISS]; in do_6xx_tlb()
573 way = (env->spr[SPR_SRR1] >> 17) & 1; in do_6xx_tlb()
679 if (env->spr[SPR_40x_PID] != val) { in helper_store_40x_pid()
680 env->spr[SPR_40x_PID] = val; in helper_store_40x_pid()
753 if ((tlb->prot & PAGE_VALID) && tlb->PID == env->spr[SPR_40x_PID]) { in helper_4xx_tlbwe_hi()
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H A Dmachine.c126 env->spr[SPR_LR] = env->lr; in cpu_pre_save()
127 env->spr[SPR_CTR] = env->ctr; in cpu_pre_save()
128 env->spr[SPR_XER] = cpu_read_xer(env); in cpu_pre_save()
130 env->spr[SPR_CFAR] = env->cfar; in cpu_pre_save()
132 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; in cpu_pre_save()
135 env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; in cpu_pre_save()
136 env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; in cpu_pre_save()
137 env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; in cpu_pre_save()
138 env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; in cpu_pre_save()
141 env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; in cpu_pre_save()
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H A Dexcp_helper.c147 miss = &env->spr[SPR_IMISS]; in ppc_excp_debug_sw_tlb()
148 cmp = &env->spr[SPR_ICMP]; in ppc_excp_debug_sw_tlb()
156 miss = &env->spr[SPR_DMISS]; in ppc_excp_debug_sw_tlb()
157 cmp = &env->spr[SPR_DCMP]; in ppc_excp_debug_sw_tlb()
162 env->spr[SPR_HASH1], env->spr[SPR_HASH2], in ppc_excp_debug_sw_tlb()
291 if (hv_escalation && !(env->spr[SPR_LPCR] & LPCR_HR)) { in ppc_excp_apply_ail()
300 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; in ppc_excp_apply_ail()
317 if (!(env->spr[SPR_LPCR] & LPCR_HAIL)) { in ppc_excp_apply_ail()
323 ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; in ppc_excp_apply_ail()
444 trace_ppc_excp_dsi(env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); in powerpc_excp_40x()
[all …]
H A Dmmu-hash32.c145 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
150 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
152 env->spr[SPR_DSISR] = 0x06000000; in ppc_hash32_direct_store()
154 env->spr[SPR_DSISR] = 0x04000000; in ppc_hash32_direct_store()
170 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
172 env->spr[SPR_DSISR] = 0x06100000; in ppc_hash32_direct_store()
174 env->spr[SPR_DSISR] = 0x04100000; in ppc_hash32_direct_store()
194 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
196 env->spr[SPR_DSISR] = 0x0a000000; in ppc_hash32_direct_store()
198 env->spr[SPR_DSISR] = 0x08000000; in ppc_hash32_direct_store()
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H A Dkvm.c211 sregs.pvr = cenv->spr[SPR_PVR]; in kvm_arch_sync_sregs()
563 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) in kvm_get_one_spr() argument
579 trace_kvm_failed_spr_get(spr, strerror(errno)); in kvm_get_one_spr()
583 env->spr[spr] = val.u32; in kvm_get_one_spr()
587 env->spr[spr] = val.u64; in kvm_get_one_spr()
597 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) in kvm_put_one_spr() argument
612 val.u32 = env->spr[spr]; in kvm_put_one_spr()
616 val.u64 = env->spr[spr]; in kvm_put_one_spr()
626 trace_kvm_failed_spr_set(spr, strerror(errno)); in kvm_put_one_spr()
874 sregs.pvr = env->spr[SPR_PVR]; in kvmppc_put_books_sregs()
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H A Dmmu_common.c63 env->spr[SPR_SDR1] = value; in ppc_store_sdr1()
164 env->spr[r] = ptem; in ppc6xx_tlb_check()
630 env->spr[SPR_40x_DEAR] = eaddr; in ppc_40x_xlate()
631 env->spr[SPR_40x_ESR] = 0x00000000; in ppc_40x_xlate()
647 env->spr[SPR_40x_DEAR] = eaddr; in ppc_40x_xlate()
649 env->spr[SPR_40x_ESR] = 0x00800000; in ppc_40x_xlate()
651 env->spr[SPR_40x_ESR] = 0x00000000; in ppc_40x_xlate()
658 env->spr[SPR_40x_DEAR] = eaddr; in ppc_40x_xlate()
660 env->spr[SPR_40x_ESR] |= 0x00800000; in ppc_40x_xlate()
711 env->spr[SPR_IMISS] = eaddr; in ppc_6xx_xlate()
[all …]
H A Dhelper_regs.c62 ((env->spr[SPR_POWER_MMCRA] & MMCRA_BHRBRD) || !pr)) { in hreg_check_bhrb_enable()
67 mmcr0 = env->spr[SPR_POWER_MMCR0]; in hreg_check_bhrb_enable()
89 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in hreg_compute_pmu_hflags_value()
148 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; in hreg_compute_hflags_value()
183 if (env->spr[SPR_LPCR] & LPCR_GTSE) { in hreg_compute_hflags_value()
186 if (env->spr[SPR_LPCR] & LPCR_HR) { in hreg_compute_hflags_value()
363 env->spr[SPR_405_SLER] = val; in store_40x_sler()
406 ppc_spr_t *spr = &env->spr_cb[num]; in _spr_register() local
409 assert(spr->name == NULL); in _spr_register()
412 spr->name = name; in _spr_register()
[all …]
H A Dmmu-radix64.c77 *pid = env->spr[SPR_BOOKS_PID]; in ppc_radix64_get_fully_qualified_addr()
80 *lpid = env->spr[SPR_LPIDR]; in ppc_radix64_get_fully_qualified_addr()
81 *pid = env->spr[SPR_BOOKS_PID]; in ppc_radix64_get_fully_qualified_addr()
84 *lpid = env->spr[SPR_LPIDR]; in ppc_radix64_get_fully_qualified_addr()
97 *lpid = env->spr[SPR_LPIDR]; in ppc_radix64_get_fully_qualified_addr()
98 *pid = env->spr[SPR_BOOKS_PID]; in ppc_radix64_get_fully_qualified_addr()
104 *lpid = env->spr[SPR_LPIDR]; in ppc_radix64_get_fully_qualified_addr()
130 env->spr[SPR_DAR] = eaddr; in ppc_radix64_raise_segi()
166 env->spr[SPR_DSISR] = cause; in ppc_radix64_raise_si()
167 env->spr[SPR_DAR] = eaddr; in ppc_radix64_raise_si()
[all …]
H A Dgdbstub.c309 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature() local
311 if (!spr->name) { in gdb_gen_spr_feature()
323 spr->gdb_id = num_regs; in gdb_gen_spr_feature()
336 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature() local
338 if (!spr->name) { in gdb_gen_spr_feature()
342 gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), in gdb_gen_spr_feature()
343 TARGET_LONG_BITS, spr->gdb_id, in gdb_gen_spr_feature()
357 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_find_spr_idx() local
359 if (spr->name && spr->gdb_id == n) { in gdb_find_spr_idx()
401 val = env->spr[reg]; in gdb_get_spr_reg()
[all …]
H A Dcpu.c101 env->spr[SPR_LPCR] = val & pcc->lpcr_mask; in ppc_store_lpcr()
112 target_ulong ciabr = env->spr[SPR_CIABR]; in ppc_update_ciabr()
130 env->spr[SPR_CIABR] = val; in ppc_store_ciabr()
139 target_ulong deaw = env->spr[spr_dawr] & PPC_BITMASK(0, 60); in ppc_update_daw()
140 uint32_t dawrx = env->spr[spr_dawrx]; in ppc_update_daw()
177 env->spr[SPR_DAWR0] = val; in ppc_store_dawr0()
191 env->spr[rid ? SPR_DAWRX1 : SPR_DAWRX0] = val; in ppc_store_dawrx()
202 env->spr[SPR_DAWR1] = val; in ppc_store_dawr1()
H A Dmmu-hash64.c449 int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; in ppc_hash64_iamr_prot()
474 amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3; in ppc_hash64_amr_prot()
522 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) { in ppc_hash64_hpt_base()
527 base = cpu->env.spr[SPR_SDR1]; in ppc_hash64_hpt_base()
542 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) { in ppc_hash64_hpt_mask()
547 base = cpu->env.spr[SPR_SDR1]; in ppc_hash64_hpt_mask()
723 if (env->spr[SPR_LPCR] & LPCR_ISL) { in ppc_hash64_htab_lookup()
816 return !!(env->spr[SPR_LPCR] & LPCR_VPM0); in ppc_hash64_use_vrma()
827 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); in ppc_hash64_set_isi()
833 env->spr[SPR_ASDR] = slb_vsid; in ppc_hash64_set_isi()
[all …]
H A Dppc-qmp-cmds.c159 ppc_spr_t *spr = &env->spr_cb[i]; in target_get_monitor_def() local
161 if (spr->name && (strcasecmp(name, spr->name) == 0)) { in target_get_monitor_def()
162 *pval = env->spr[i]; in target_get_monitor_def()
H A Duser_only_helper.c48 env->spr[SPR_DAR] = address; in ppc_cpu_record_sigsegv()
49 env->spr[SPR_DSISR] = error_code; in ppc_cpu_record_sigsegv()
H A Dmmu-book3s-v3.c28 uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; in ppc64_v3_get_pate()
29 uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; in ppc64_v3_get_pate()
H A Dmmu-book3s-v3.h67 return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT); in ppc64_use_proc_tbl()
80 return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR); in ppc64_v3_radix()
H A Dcpu_init.c2107 if (env->spr[SPR_HID0] & 0x00E00000) { in check_pow_hid0()
2116 if (env->spr[SPR_HID0] & 0x00600000) { in check_pow_hid0_74xx()
2126 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { in check_attn_hid0()
2135 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { in check_attn_hid0_power9()
2887 env->spr[SPR_PVR]); in init_proc_e500()
2912 env->spr[SPR_PVR]); in init_proc_e500()
5088 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { in check_pow_970()
7339 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_cpu_reset_hold() local
7341 if (!spr->name) { in ppc_cpu_reset_hold()
7344 env->spr[i] = spr->default_value; in ppc_cpu_reset_hold()
[all …]
/qemu/hw/ppc/
H A Dspapr_nested.c152 save->lpcr = env->spr[SPR_LPCR]; in nested_save_state()
153 save->lpidr = env->spr[SPR_LPIDR]; in nested_save_state()
154 save->pcr = env->spr[SPR_PCR]; in nested_save_state()
155 save->dpdes = env->spr[SPR_DPDES]; in nested_save_state()
156 save->hfscr = env->spr[SPR_HFSCR]; in nested_save_state()
157 save->srr0 = env->spr[SPR_SRR0]; in nested_save_state()
158 save->srr1 = env->spr[SPR_SRR1]; in nested_save_state()
159 save->sprg0 = env->spr[SPR_SPRG0]; in nested_save_state()
160 save->sprg1 = env->spr[SPR_SPRG1]; in nested_save_state()
161 save->sprg2 = env->spr[SPR_SPRG2]; in nested_save_state()
[all …]
H A Dppc_booke.c92 (env->spr[SPR_BOOKE_TSR] & TSR_DIS in booke_update_irq()
93 && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); in booke_update_irq()
96 (env->spr[SPR_BOOKE_TSR] & TSR_WIS in booke_update_irq()
97 && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); in booke_update_irq()
100 (env->spr[SPR_BOOKE_TSR] & TSR_FIS in booke_update_irq()
101 && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); in booke_update_irq()
108 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; in booke_get_fit_target()
112 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) in booke_get_fit_target()
126 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; in booke_get_wdt_target()
130 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) in booke_get_wdt_target()
[all …]
H A Dppc.c287 dbsr = env->spr[SPR_40x_DBSR]; in ppc40x_core_reset()
290 env->spr[SPR_40x_DBSR] = dbsr; in ppc40x_core_reset()
301 dbsr = env->spr[SPR_40x_DBSR]; in ppc40x_chip_reset()
304 env->spr[SPR_40x_DBSR] = dbsr; in ppc40x_chip_reset()
522 return env->spr[SPR_TBL]; in cpu_ppc_load_tbl()
547 return env->spr[SPR_TBU]; in cpu_ppc_load_tbu()
756 if (env->spr[SPR_LPCR] & LPCR_LD) { in _cpu_ppc_load_decr()
767 return env->spr[SPR_DECR]; in cpu_ppc_load_decr()
920 if (env->spr[SPR_LPCR] & LPCR_LD) { in cpu_ppc_store_decr()
1200 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { in cpu_4xx_fit_cb()
[all …]
H A Dspapr_cpu_core.c52 env->spr[SPR_HIOR] = 0; in spapr_reset_vcpu()
54 lpcr = env->spr[SPR_LPCR]; in spapr_reset_vcpu()
67 env->spr[SPR_PSSCR] |= PSSCR_EC; in spapr_reset_vcpu()
72 env->spr[SPR_AMOR] = 0xffffffffffffffffull; in spapr_reset_vcpu()
103 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); in spapr_cpu_set_entry_state()
/qemu/target/openrisc/
H A Dsys_helper.c43 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) in HELPER()
53 switch (spr) { in HELPER()
64 switch (spr) { in HELPER()
97 idx = (spr - 1024); in HELPER()
102 idx = spr - TO_SPR(1, 512); in HELPER()
113 idx = spr - TO_SPR(1, 640); in HELPER()
125 idx = spr - TO_SPR(2, 512); in HELPER()
136 idx = spr - TO_SPR(2, 640); in HELPER()
217 target_ulong spr) in HELPER()
228 switch (spr) { in HELPER()
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