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Searched refs:pir (Results 1 – 18 of 18) sorted by relevance

/qemu/include/hw/ppc/
H A Dpnv_chip.h106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
107 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
140 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
141 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
142 #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f)) argument
161 uint32_t *pir, uint32_t *tir);
H A Dpnv_core.h61 uint32_t pir; member
H A Dopenpic.h156 uint32_t pir; /* Processor initialization register */ member
H A Dppc.h7 PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
H A Dpnv.h61 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
/qemu/tests/qtest/
H A Dpnv-xive2-test.c67 static void set_tima8(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima8() argument
72 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima8()
76 static void set_tima32(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima32() argument
81 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima32()
85 static uint8_t get_tima8(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima8() argument
89 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima8()
93 static uint16_t get_tima16(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima16() argument
97 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima16()
101 static uint32_t get_tima32(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima32() argument
105 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima32()
/qemu/hw/ppc/
H A Dpnv.c150 uint32_t pir, tir; in pnv_dt_core() local
161 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
166 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); in pnv_dt_core()
173 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); in pnv_dt_core()
174 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); in pnv_dt_core()
248 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
249 servers_prop[i * 2] = cpu_to_be32(pir); in pnv_dt_core()
251 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
252 servers_prop[i * 2 + 1] = cpu_to_be32(pir); in pnv_dt_core()
260 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
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H A Dppce500_spin.c46 uint32_t pir; member
68 stl_p(&info->pir, i); in spin_reset()
82 stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); in spin_kick()
H A Dpnv_core.c309 uint32_t pir, tir; in pnv_core_cpu_realize() local
325 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); in pnv_core_cpu_realize()
326 pir_spr->default_value = pir; in pnv_core_cpu_realize()
H A Dppc.c1534 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) in ppc_get_vcpu_by_pir() argument
1541 if (ppc_cpu_pir(cpu) == pir) { in ppc_get_vcpu_by_pir()
/qemu/hw/intc/
H A Dpnv_xive2.c410 int pir = pnv_xive2_get_current_pir(xive); in pnv_xive2_inject_notify() local
411 int thread_nr = PNV10_PIR2THREAD(pir); in pnv_xive2_inject_notify()
412 int thread_topo_id = PNV10_PIR2CHIP(pir); in pnv_xive2_inject_notify()
617 int pir = ppc_cpu_pir(cpu); in pnv_xive2_is_cpu_enabled() local
618 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); in pnv_xive2_is_cpu_enabled()
620 uint32_t bit = pir & 0x3f; in pnv_xive2_is_cpu_enabled()
761 int pir = ppc_cpu_pir(cpu); in pnv_xive2_tm_get_xive() local
766 xive2_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive2_tm_get_xive()
2098 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) in pnv_xive2_get_indirect_tctx() argument
2103 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive2_get_indirect_tctx()
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H A Dpnv_xive.c465 int pir = ppc_cpu_pir(cpu); in pnv_xive_is_cpu_enabled() local
466 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); in pnv_xive_is_cpu_enabled()
468 uint32_t bit = pir & 0x3f; in pnv_xive_is_cpu_enabled()
548 int pir = ppc_cpu_pir(cpu); in pnv_xive_tm_get_xive() local
553 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_tm_get_xive()
1578 int pir; in pnv_xive_get_indirect_tctx() local
1585 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); in pnv_xive_get_indirect_tctx()
1586 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive_get_indirect_tctx()
1588 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); in pnv_xive_get_indirect_tctx()
1594 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_get_indirect_tctx()
H A Dxive2.c499 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_ctx() local
528 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { in xive2_tctx_save_ctx()
531 nvp_blk, nvp_idx, pir); in xive2_tctx_save_ctx()
578 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line() local
584 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); in xive2_tctx_hw_cam_line()
749 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx() local
769 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); in xive2_tctx_restore_os_ctx()
H A Dopenpic.c596 if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { in openpic_gbl_write()
600 } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { in openpic_gbl_write()
606 opp->pir = val; in openpic_gbl_write()
1265 opp->pir = 0; in openpic_reset()
1474 VMSTATE_UINT32(pir, OpenPICState),
H A Dxive.c1652 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive_tctx_hw_cam_line() local
1655 return xive_nvt_cam_line(blk, 1 << 7 | (pir & 0x7f)); in xive_tctx_hw_cam_line()
/qemu/target/ppc/
H A Dtcg-excp_helper.c688 int pir = rb & DBELL_PIRTAG_MASK; in helper_msgsnd() local
700 if ((rb & DBELL_BRDCAST_MASK) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { in helper_msgsnd()
768 int pir = rb & DBELL_PROCIDTAG_MASK; in helper_book3s_msgsnd() local
784 cpu = ppc_get_vcpu_by_pir(pir); in helper_book3s_msgsnd()
H A Dkvm.c1055 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; in kvmppc_get_booke_sregs()
/qemu/linux-headers/asm-powerpc/
H A Dkvm.h209 __u32 pir; /* read-only */ member