410     int pir = pnv_xive2_get_current_pir(xive);  in pnv_xive2_inject_notify()  local
411     int thread_nr = PNV10_PIR2THREAD(pir);  in pnv_xive2_inject_notify()
412     int thread_topo_id = PNV10_PIR2CHIP(pir);  in pnv_xive2_inject_notify()
617     int pir = ppc_cpu_pir(cpu);  in pnv_xive2_is_cpu_enabled()  local
618     uint32_t fc = PNV10_PIR2FUSEDCORE(pir);  in pnv_xive2_is_cpu_enabled()
620     uint32_t bit = pir & 0x3f;  in pnv_xive2_is_cpu_enabled()
761     int pir = ppc_cpu_pir(cpu);  in pnv_xive2_tm_get_xive()  local
766         xive2_error(xive, "IC: CPU %x is not enabled", pir);  in pnv_xive2_tm_get_xive()
2098 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir)  in pnv_xive2_get_indirect_tctx()  argument
2103     cpu = pnv_chip_find_cpu(chip, pir);  in pnv_xive2_get_indirect_tctx()
2105         xive2_error(xive, "IC: invalid PIR %x for indirect access", pir);  in pnv_xive2_get_indirect_tctx()
2110         xive2_error(xive, "IC: CPU %x is not enabled", pir);  in pnv_xive2_get_indirect_tctx()
2122     uint32_t pir;  in pnv_xive2_ic_tm_indirect_read()  local
2126     pir = pnv_xive2_ic_tm_get_pir(xive, offset);  in pnv_xive2_ic_tm_indirect_read()
2128     tctx = pnv_xive2_get_indirect_tctx(xive, pir);  in pnv_xive2_ic_tm_indirect_read()
2142     uint32_t pir;  in pnv_xive2_ic_tm_indirect_write()  local
2145     pir = pnv_xive2_ic_tm_get_pir(xive, offset);  in pnv_xive2_ic_tm_indirect_write()
2147     tctx = pnv_xive2_get_indirect_tctx(xive, pir);  in pnv_xive2_ic_tm_indirect_write()