| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
124 interrupts = <11 1>;
143 interrupts = <0x1d 0x4>;
159 interrupts = < /*TXEOB*/ 0x6 0x4
169 interrupts = <0x1d 4>;
177 interrupts = <0x1e 4>;
187 interrupts = <0x0 0x1 0x2>;
197 interrupts = <0x5 0x4>;
[all …]
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| H A D | bamboo.dts | 97 interrupts = <7 4>;
106 interrupts = <5 1>;
118 interrupts = <0 4>;
129 interrupts = <1 4>;
137 interrupts = <2 4>;
145 interrupts = <7 4>;
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| H A D | petalogix-s3adsp1800.dts | 121 interrupts = <0x01 0x00>;
214 interrupts = <0x02 0x02>;
236 interrupts = <0x03 0x00>;
271 interrupts = <0x00 0x02>;
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| H A D | petalogix-ml605.dts | 145 interrupts = < 0x03 0x02 >;
183 interrupts = < 0x01 0x02 0x00 0x02 >;
206 interrupts = < 0x05 0x02 >;
223 interrupts = < 0x02 0x00 >;
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| /qemu/docs/specs/ |
| H A D | vmw_pvscsi-spec.rst | 18 The registers area is used to raise hypervisor interrupts and issue device
30 issue device interrupts, and control interrupt masking.
55 Completion interrupts (completion ring notifications):
60 Message interrupts (message ring notifications):
70 In the case of legacy interrupts, the ``PVSCSI_REG_OFFSET_INTR_STATUS``
90 f. Unmask completion and message (if device messages enabled) interrupts
95 a. Mask interrupts
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| H A D | ivshmem-spec.rst | 43 kernel driver to handle interrupts. Requires the device to be
44 configured for interrupts, obviously.
47 configured for interrupts. It becomes safely accessible only after
54 it is configured for interrupts.
89 IVPosition Register: if the device is not configured for interrupts,
96 configured for interrupts. A positive IVPosition means interrupts,
103 If the device is not configured for interrupts, the write is ignored.
130 When configured for interrupts, the peers share eventfd objects in
146 (these contain file descriptors for sending interrupts),
150 descriptors for receiving interrupts).
[all …]
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| H A D | acpi_hw_reduced_hotplug.rst | 11 GED allows HW reduced platforms to handle interrupts in ACPI ASL
13 from GPIO events. All interrupts are listed in _CRS and the handler
|
| H A D | aspeed-intc.rst | 8 interrupt numbers of processors, the interrupts are merged every 32 sources for
21 Currently, only GIC 192 to 201 are supported, and their source interrupts are
|
| H A D | ppc-xive.rst | 11 deliver interrupts directly to virtual processors without hypervisor
20 processing layer of external interrupts:
76 Each of the sub-engines uses a set of tables to redirect interrupts
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| H A D | edu.rst | 76 generating interrupts.
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| /qemu/hw/dma/ |
| H A D | omap_dma.c | 57 int interrupts; member
414 if (ch->interrupts & LAST_FRAME_INTR) in omap_dma_transfer_generic()
420 if (ch->interrupts & HALF_FRAME_INTR) in omap_dma_transfer_generic()
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) in omap_dma_transfer_generic()
455 if (ch->interrupts & END_FRAME_INTR) in omap_dma_transfer_generic()
478 if (ch->interrupts & END_BLOCK_INTR) in omap_dma_transfer_generic()
516 if (ch->interrupts & TIMEOUT_INTR)
549 (ch->interrupts & LAST_FRAME_INTR) &&
555 ch->interrupts & HALF_FRAME_INTR,
561 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
[all …]
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| /qemu/hw/display/ |
| H A D | omap_lcdc.c | 40 int interrupts; member
55 if (s->frame_done && (s->interrupts & 1)) { in omap_lcd_interrupts()
60 if (s->palette_done && (s->interrupts & 2)) { in omap_lcd_interrupts()
287 if (omap_lcd->dma->interrupts & 1) in omap_update_display()
361 if (s->dma->interrupts & (1 << 1)) in omap_lcd_update()
386 (s->tft << 7) | (s->interrupts << 3) | in omap_lcdc_read()
420 s->interrupts = (value >> 3) & 3; in omap_lcdc_write()
470 s->interrupts = 0; in omap_lcdc_reset()
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| /qemu/tests/qtest/libqos/ |
| H A D | ahci.c | 48 uint32_t interrupts; /* Expected interrupts for this command. */ member
89 uint32_t interrupts; member
419 reg &= ~cmd->interrupts; in ahci_port_check_error()
478 ASSERT_BIT_SET(reg, cmd->interrupts); in ahci_port_check_interrupts()
481 ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts); in ahci_port_check_interrupts()
923 cmd->interrupts = AHCI_PX_IS_DHRS; in ahci_command_create()
929 cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0; in ahci_command_create()
946 cmd->interrupts |= bcl ? AHCI_PX_IS_PSS : 0; in ahci_atapi_command_create()
957 cmd->interrupts |= AHCI_PX_IS_TFES; in ahci_atapi_test_ready()
1161 cmd->interrupts |= AHCI_PX_IS_PSS; in ahci_command_set_sizes()
[all …]
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| /qemu/docs/system/devices/ |
| H A D | ivshmem.rst | 18 If desired, interrupts can be sent between guest VMs accessing the same
34 allows guests using the same server to communicate via interrupts.
|
| H A D | ivshmem-flat.rst | 13 notification via HW interrupts and Inter-VM shared memory. This allows the
25 Although the ivshmem-flat supports both peer notification (interrupts) and
|
| H A D | igb.rst | 59 ethtool can test register accesses, interrupts, etc. It is automated as an
|
| /qemu/hw/ppc/ |
| H A D | spapr_events.c | 385 uint32_t interrupts[2]; in spapr_dt_events() local
394 spapr_dt_irq(interrupts, source->irq, false); in spapr_dt_events()
397 _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, in spapr_dt_events()
398 sizeof(interrupts))); in spapr_dt_events()
400 irq_ranges[count++] = interrupts[0]; in spapr_dt_events()
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| /qemu/rust/hw/char/pl011/src/ |
| H A D | device.rs | 109 /// QEMU interrupts
121 pub interrupts: [InterruptSource; IRQMASK.len()], field
306 // interrupts always checked in write_data_register()
361 // Change interrupts based on updated FR in loopback_mdmctrl()
529 for irq in self.interrupts.iter() { in post_init()
634 for (irq, i) in self.interrupts.iter().zip(IRQMASK) { in update()
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| /qemu/docs/system/arm/ |
| H A D | b-l475e-iot01a.rst | 18 - STM32L4x5 EXTI (Extended interrupts and events controller)
|
| /qemu/docs/system/riscv/ |
| H A D | virt.rst | 127 interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
128 message signaled interrupt controller) to handle both wired interrupts and
130 SiFive PLIC to handle wired interrupts.
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| /qemu/docs/system/i386/ |
| H A D | kvm-pv.rst | 78 Support 'Extended Destination ID' for external interrupts. The feature allows
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| /qemu/docs/devel/ |
| H A D | multi-process.rst | 141 directly inject interrupts into the VM via the KVM driver, again,
170 emulation application, using a file descriptor to inject interrupts into
384 A proxy for a device that generates interrupts will need to create a
461 (such as interrupts or IOMMU mappings) back to the QEMU process.
517 - PCI pin interrupts
528 - PCI MSI/X interrupts
530 PCI MSI/X interrupts are implemented in HW as DMA writes to a
844 Traditional PCI pin interrupts are level based, so, in addition to an
874 MSI/X interrupts are sent as DMA transactions to the host. The interrupt
876 multiple MSI interrupts associated with it, so multiple irq descriptors
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| /qemu/docs/ |
| H A D | pci_expander_bridge.txt | 50 The interrupts from devices behind the PXB are routed through this device the same as if it were a
|
| /qemu/docs/system/ |
| H A D | replay.rst | 18 including external input, hardware clocks, and interrupts.
81 simulated hardware, memory of VM, software interrupts, and execution of
|
| /qemu/hw/arm/ |
| H A D | omap1.c | 2540 uint8_t interrupts; member
2637 return s->interrupts; in omap_rtc_read()
2773 s->interrupts = value; in omap_rtc_write()
2814 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { in omap_rtc_tick()
2819 if (s->interrupts & 0x04) in omap_rtc_tick()
2820 switch (s->interrupts & 3) { in omap_rtc_tick()
2865 s->interrupts = 0; in omap_rtc_reset()
|