48     uint32_t interrupts; /* Expected interrupts for this command. */  member
89     uint32_t interrupts;  member
419         reg &= ~cmd->interrupts;  in ahci_port_check_error()
478     ASSERT_BIT_SET(reg, cmd->interrupts);  in ahci_port_check_interrupts()
481     ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts);  in ahci_port_check_interrupts()
923         cmd->interrupts = AHCI_PX_IS_DHRS;  in ahci_command_create()
929     cmd->interrupts |= props->ncq ? AHCI_PX_IS_SDBS : 0;  in ahci_command_create()
946         cmd->interrupts |= bcl ? AHCI_PX_IS_PSS : 0;  in ahci_atapi_command_create()
957         cmd->interrupts |= AHCI_PX_IS_TFES;  in ahci_atapi_test_ready()
1161             cmd->interrupts |= AHCI_PX_IS_PSS;  in ahci_command_set_sizes()
1287     if (cmd->interrupts & AHCI_PX_IS_DHRS) {  in ahci_command_verify()