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Searched refs:hartid_base (Results 1 – 10 of 10) sorted by relevance

/qemu/hw/intc/
H A Driscv_aclint.c70 hartid = hartid - mtimer->hartid_base; in riscv_aclint_mtimer_write_timecmp()
131 size_t hartid = mtimer->hartid_base + in riscv_aclint_mtimer_read()
174 size_t hartid = mtimer->hartid_base + in riscv_aclint_mtimer_write()
235 CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i); in riscv_aclint_mtimer_write()
241 mtimer->hartid_base + i, in riscv_aclint_mtimer_write()
267 hartid_base, 0),
295 RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); in riscv_aclint_mtimer_realize()
352 uint32_t hartid_base, uint32_t num_harts, in riscv_aclint_mtimer_create() argument
365 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aclint_mtimer_create()
375 CPUState *cpu = cpu_by_arch_id(hartid_base + i); in riscv_aclint_mtimer_create()
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H A Dsifive_plic.c127 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update()
130 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update()
334 addrid = 0, hartid = plic->hartid_base; in parse_hart_config()
402 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i)); in sifive_plic_realize()
435 DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
478 uint32_t hartid_base, uint32_t num_sources, in type_init()
491 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in type_init()
511 qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts, in type_init()
515 qdev_connect_gpio_out(dev, cpu_num - hartid_base, in type_init()
H A Driscv_aplic.c904 cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); in riscv_aplic_realize()
957 DEFINE_PROP_UINT32("hartid-base", RISCVAPLICState, hartid_base, 0),
1047 uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, in riscv_aplic_create() argument
1060 qdev_prop_set_uint32(dev, "hartid-base", hartid_base); in riscv_aplic_create()
1078 CPUState *cpu = cpu_by_arch_id(hartid_base + i); in riscv_aplic_create()
/qemu/include/hw/intc/
H A Driscv_aclint.h40 uint32_t hartid_base; member
50 uint32_t hartid_base, uint32_t num_harts,
65 uint32_t hartid_base; member
71 DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
H A Dsifive_plic.h64 uint32_t hartid_base; member
81 uint32_t hartid_base, uint32_t num_sources,
H A Driscv_aplic.h65 uint32_t hartid_base; member
84 uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
/qemu/hw/riscv/
H A Driscv_hart.c35 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
143 s->harts[idx].env.mhartid = s->hartid_base + idx; in riscv_hart_realize()
H A Dspike.c109 s->soc[socket].hartid_base + cpu); in create_fdt()
120 s->soc[socket].hartid_base + cpu); in create_fdt()
H A Dvirt.c252 s->soc[socket].hartid_base + cpu); in create_fdt_socket_cpus()
281 s->soc[socket].hartid_base + cpu); in create_fdt_socket_cpus()
/qemu/include/hw/riscv/
H A Driscv_hart.h38 uint32_t hartid_base; member