70     hartid = hartid - mtimer->hartid_base;  in riscv_aclint_mtimer_write_timecmp()
131         size_t hartid = mtimer->hartid_base +  in riscv_aclint_mtimer_read()
174         size_t hartid = mtimer->hartid_base +  in riscv_aclint_mtimer_write()
235             CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);  in riscv_aclint_mtimer_write()
241                                               mtimer->hartid_base + i,  in riscv_aclint_mtimer_write()
267         hartid_base, 0),
295         RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));  in riscv_aclint_mtimer_realize()
352     uint32_t hartid_base, uint32_t num_harts,  in riscv_aclint_mtimer_create()  argument
365     qdev_prop_set_uint32(dev, "hartid-base", hartid_base);  in riscv_aclint_mtimer_create()
375         CPUState *cpu = cpu_by_arch_id(hartid_base + i);  in riscv_aclint_mtimer_create()
409         size_t hartid = swi->hartid_base + (addr >> 2);  in riscv_aclint_swi_read()
432         size_t hartid = swi->hartid_base + (addr >> 2);  in riscv_aclint_swi_write()
440                 qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]);  in riscv_aclint_swi_write()
443                     qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]);  in riscv_aclint_swi_write()
465     DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0),
484         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));  in riscv_aclint_swi_realize()
531 DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,  in riscv_aclint_swi_create()  argument
540     qdev_prop_set_uint32(dev, "hartid-base", hartid_base);  in riscv_aclint_swi_create()
547         CPUState *cpu = cpu_by_arch_id(hartid_base + i);  in riscv_aclint_swi_create()