| /qemu/tcg/arm/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/i386/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/sparc64/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/aarch64/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/s390x/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/tci/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ |
| H A D | tcg-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-op.c | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg.c | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/mips/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ppc/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/loongarch64/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/riscv/ |
| H A D | tcg-target-has.h | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | 937246f2ee87d01062bac7c356c1766b8c5038a8 Tue Jan 07 18:16:03 UTC 2025 Richard Henderson <richard.henderson@linaro.org> tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|