1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Define target-specific opcode support
4 * Copyright (c) 2008 Fabrice Bellard
5 */
6
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9
10 #include "host/cpuinfo.h"
11
12 #define have_bmi1 (cpuinfo & CPUINFO_BMI1)
13 #define have_popcnt (cpuinfo & CPUINFO_POPCNT)
14 #define have_avx1 (cpuinfo & CPUINFO_AVX1)
15 #define have_avx2 (cpuinfo & CPUINFO_AVX2)
16 #define have_movbe (cpuinfo & CPUINFO_MOVBE)
17
18 /*
19 * There are interesting instructions in AVX512, so long as we have AVX512VL,
20 * which indicates support for EVEX on sizes smaller than 512 bits.
21 */
22 #define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \
23 (cpuinfo & CPUINFO_AVX512F))
24 #define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
25 #define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
26 #define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
27
28 /* optional instructions */
29 #if TCG_TARGET_REG_BITS == 64
30 /* Keep 32-bit values zero-extended in a register. */
31 #define TCG_TARGET_HAS_extr_i64_i32 1
32 #endif
33
34 #define TCG_TARGET_HAS_qemu_ldst_i128 \
35 (TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
36
37 #define TCG_TARGET_HAS_tst 1
38
39 /* We do not support older SSE systems, only beginning with AVX1. */
40 #define TCG_TARGET_HAS_v64 have_avx1
41 #define TCG_TARGET_HAS_v128 have_avx1
42 #define TCG_TARGET_HAS_v256 have_avx2
43
44 #define TCG_TARGET_HAS_andc_vec 1
45 #define TCG_TARGET_HAS_orc_vec have_avx512vl
46 #define TCG_TARGET_HAS_nand_vec have_avx512vl
47 #define TCG_TARGET_HAS_nor_vec have_avx512vl
48 #define TCG_TARGET_HAS_eqv_vec have_avx512vl
49 #define TCG_TARGET_HAS_not_vec have_avx512vl
50 #define TCG_TARGET_HAS_neg_vec 0
51 #define TCG_TARGET_HAS_abs_vec 1
52 #define TCG_TARGET_HAS_roti_vec have_avx512vl
53 #define TCG_TARGET_HAS_rots_vec 0
54 #define TCG_TARGET_HAS_rotv_vec have_avx512vl
55 #define TCG_TARGET_HAS_shi_vec 1
56 #define TCG_TARGET_HAS_shs_vec 1
57 #define TCG_TARGET_HAS_shv_vec have_avx2
58 #define TCG_TARGET_HAS_mul_vec 1
59 #define TCG_TARGET_HAS_sat_vec 1
60 #define TCG_TARGET_HAS_minmax_vec 1
61 #define TCG_TARGET_HAS_bitsel_vec have_avx512vl
62 #define TCG_TARGET_HAS_cmpsel_vec 1
63 #define TCG_TARGET_HAS_tst_vec have_avx512bw
64
65 #define TCG_TARGET_deposit_valid(type, ofs, len) \
66 (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
67 (TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
68
69 /*
70 * Check for the possibility of low byte/word extraction, high-byte extraction
71 * and zero-extending 32-bit right-shift.
72 *
73 * We cannot sign-extend from high byte to 64-bits without using the
74 * REX prefix that explicitly excludes access to the high-byte registers.
75 */
76 static inline bool
tcg_target_sextract_valid(TCGType type,unsigned ofs,unsigned len)77 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
78 {
79 switch (ofs) {
80 case 0:
81 switch (len) {
82 case 8:
83 case 16:
84 return true;
85 case 32:
86 return type == TCG_TYPE_I64;
87 }
88 return false;
89 case 8:
90 return len == 8 && type == TCG_TYPE_I32;
91 }
92 return false;
93 }
94 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid
95
96 static inline bool
tcg_target_extract_valid(TCGType type,unsigned ofs,unsigned len)97 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
98 {
99 if (type == TCG_TYPE_I64 && ofs + len == 32) {
100 return true;
101 }
102 switch (ofs) {
103 case 0:
104 return len == 8 || len == 16;
105 case 8:
106 return len == 8;
107 }
108 return false;
109 }
110 #define TCG_TARGET_extract_valid tcg_target_extract_valid
111
112 #endif
113