/linux-5.10/arch/openrisc/kernel/ |
D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 25 #include <asm/asm-offsets.h> 46 l.sw -8(r1),r2 /* store frame pointer */ ;\ 47 l.sw -4(r1),r9 /* store return address */ ;\ 50 l.addi r1,r1,-8 ;\ 52 l.lwz r9,-4(r1) /* restore return address */ ;\ 53 l.lwz r2,-8(r1) /* restore fp */ ;\ 59 l.sw -12(r1),t1 /* save extra reg */ ;\ 60 l.sw -8(r1),r2 /* store frame pointer */ ;\ [all …]
|
D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 26 #include <asm/asm-offsets.h> 30 l.movhi rd,hi(-KERNELBASE) ;\ 73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4 76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5 79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6 82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7 85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8 88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9 [all …]
|
/linux-5.10/arch/x86/math-emu/ |
D | errors.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /*---------------------------------------------------------------------------+ 5 | The error handling functions for wm-FPU-emu | 9 | E-mail billm@jacobi.maths.monash.edu.au | 12 +---------------------------------------------------------------------------*/ 14 /*---------------------------------------------------------------------------+ 19 +---------------------------------------------------------------------------*/ 27 #include "exception.h" 68 EXCEPTION(EX_Invalid); 126 printk("SW: backward compatibility\n"); in FPU_printall() [all …]
|
/linux-5.10/arch/parisc/math-emu/ |
D | driver.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Linux/PA-RISC Project (http://www.parisc-linux.org/) 5 * Floating-point emulation code 6 * Copyright (C) 2001 Hewlett-Packard (Paul Bame) <bame@debian.org> 9 * linux/arch/math-emu/driver.c.c 14 * Copyright (C) 2001 Hewlett-Packard <bame@debian.org> 20 #include "math-emu.h" 25 #define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1)) 29 /* Format of the floating-point exception registers. */ 31 unsigned int exception : 6; member [all …]
|
/linux-5.10/arch/mips/kernel/ |
D | genex.S | 6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle 28 * General exception vector for all other CPUs. 31 * to fit into space reserved for the exception handler. 47 * General exception handler for CPUs with virtual coherency exception. 50 * exception) bytes to fit into space reserved for the exception handler. 75 * c0_badvaddr because after return from this exception handler the 76 * load / store will be re-executed. 80 li k1, -4 # Is this ... 89 sw k1, (k0) 100 sw k1, (k0) [all …]
|
D | cps-vec-ns16550.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 9 #include <asm/asm-offsets.h> 25 # define UART_S sw 32 * _mips_cps_putc() - write a character to the UART 45 * _mips_cps_puts() - write a string to the UART 46 * @a0: pointer to NULL-terminated ASCII string 49 * Write a null-terminated ASCII string to the UART. 65 * _mips_cps_putx4 - write a 4b hex value to the UART 76 addiu a0, a0, -10 82 * _mips_cps_putx8 - write an 8b hex value to the UART [all …]
|
/linux-5.10/Documentation/devicetree/bindings/net/wireless/ |
D | qcom,ath11k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 5 --- 7 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 - Kalle Valo <kvalo@codeaurora.org> 21 - qcom,ipq8074-wifi 22 - qcom,ipq6018-wifi 29 - description: misc-pulse1 interrupt events 30 - description: misc-latch interrupt events 31 - description: sw exception interrupt events [all …]
|
/linux-5.10/arch/mips/dec/prom/ |
D | locore.S | 1 /* SPDX-License-Identifier: GPL-2.0 */ 12 * Simple general exception handling routine. This one is used for the 23 sw k0, 0(k1)
|
/linux-5.10/arch/arm/mach-berlin/ |
D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Antoine Ténart <antoine.tenart@free-electrons.com> 20 * There are two reset registers, one with self-clearing (SC) 21 * reset and one with non-self-clearing reset (NON_SC). 47 return -EFAULT; in berlin_boot_secondary() 51 * exception vector. in berlin_boot_secondary() 64 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in berlin_smp_prepare_cpus() 70 np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl"); in berlin_smp_prepare_cpus() 84 * in the reset exception vector. in berlin_smp_prepare_cpus() 89 * Write the secondary startup address into the SW reset address in berlin_smp_prepare_cpus() [all …]
|
/linux-5.10/arch/ia64/kernel/ |
D | unaligned.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Architecture-specific unaligned trap handling. 5 * Copyright (C) 1999-2002, 2004 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 9 * 2002/12/09 Fix rotating register handling (off-by-1 error, missing fr-rotation). Fix 10 * get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame 28 #include <asm/exception.h> 69 * For M-unit: 72 * --------|------|---------| 73 * [40-37] | [36] | [35:30] | [all …]
|
/linux-5.10/arch/m68k/kernel/ |
D | signal.c | 16 * 1997-12-01 Modified for POSIX.1b signals by Andreas Schwab 25 * Atari :-) Current limitation: Only one sigstack can be active at one time. 68 [1] = -1, /* sizeof_field(struct frame, un.fmt1), */ 72 [5] = -1, /* sizeof_field(struct frame, un.fmt5), */ 73 [6] = -1, /* sizeof_field(struct frame, un.fmt6), */ 75 [8] = -1, /* sizeof_field(struct frame, un.fmt8), */ 79 [12] = -1, /* sizeof_field(struct frame, un.fmtc), */ 80 [13] = -1, /* sizeof_field(struct frame, un.fmtd), */ 81 [14] = -1, /* sizeof_field(struct frame, un.fmte), */ 82 [15] = -1, /* sizeof_field(struct frame, un.fmtf), */ [all …]
|
/linux-5.10/arch/riscv/kernel/ |
D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 14 #include <asm/asm-offsets.h> 35 addi sp, sp, -(PT_SIZE_ON_STACK) 67 * Disable user-mode memory access as it should only be set in the 89 * Set the scratch register to 0, so that if a recursive exception 90 * occurs, the exception vector knows it came from the kernel 150 /* Check if exception code lies within bounds */ 159 /* Recover a0 - a7 for system calls */ 191 * Check if syscall is rejected by tracer, i.e., a7 == -1. 194 li t1, -1 [all …]
|
/linux-5.10/arch/arc/mm/ |
D | tlbex.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * TLB Exception Handling for ARC 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 8 * -MMU v1: moved out legacy code into a seperate file 9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB 14 * entry, so that it doesn't knock out it's I-TLB entry 15 * -Some more fine tuning: 19 * -Practically rewrote the I/D TLB Miss handlers 26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing [all …]
|
/linux-5.10/arch/powerpc/mm/nohash/ |
D | tlb_low_64e.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 5 * Copyright (C) 2008-2009 15 #include <asm/asm-offsets.h> 17 #include <asm/exception-64e.h> 18 #include <asm/ppc-opcode.h> 21 #include <asm/feature-fixups.h> 36 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not 99 /* We pre-test some combination of permissions to avoid double 120 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 121 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */ [all …]
|
/linux-5.10/drivers/edac/ |
D | cpc925_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only 34 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr)) 50 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02". 57 * Processor Interface Exception Mask Register (APIMASK) 61 APIMASK_DART = CPC925_BIT(0), /* DART Exception */ 64 APIMASK_STAT = CPC925_BIT(3), /* Status Exception */ 65 APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */ 66 APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */ 67 APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */ 83 * Processor Interface Exception Register (APIEXCP) [all …]
|
/linux-5.10/arch/nds32/ |
D | Kconfig.cpu | 1 # SPDX-License-Identifier: GPL-2.0-only 17 fpu exception handler. 40 possibly significant due to additional FPU exception. 50 A set of Zero-Overhead Loop mechanism is provided to reduce the 51 instruction fetch and execution overhead of loop-control instructions. 102 prompt "Paging -- page size " 111 bool "Disable I-Cache" 117 bool "Disable D-Cache" 123 bool "Force write through D-cache" 133 Say Y here to enable write-back memory with no-write-allocation policy. [all …]
|
/linux-5.10/arch/m68k/fpsp040/ |
D | x_unfl.S | 4 | fpsp_unfl --- FPSP handler for underflow exception 7 | For 881/2 compatibility, sw must denormalize the intermediate 46 link %a6,#-LOCAL_SIZE 47 fsave -(%a7) 48 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 49 fmovemx %fp0-%fp3,USER_FP0(%a6) 56 | exception 73 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 74 fmovemx USER_FP0(%a6),%fp0-%fp3 92 | Inexact enabled and reported, and we must take an inexact exception [all …]
|
/linux-5.10/arch/microblaze/kernel/ |
D | head.S | 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 12 * Low-level exception handers, MMU support, and rewrite. 15 * Copyright (c) 1998-1999 TiVo, Inc. 75 * r8 == 0 - msr instructions are implemented 76 * r8 != 0 - msr instructions are not implemented 79 msrclr r8, 0 /* clear nothing - just read msr for test */ 85 is broken or non-existent */ 89 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ [all …]
|
/linux-5.10/arch/arm/include/asm/ |
D | uaccess-asm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 6 #include <asm/asm-offsets.h> 21 adds \tmp, \addr, #\size - 1 34 subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr 36 subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) } 45 * Whenever we re-enter userspace, the domains should always be 59 * Whenever we re-enter userspace, the domains should always be 77 * Save the address limit on entry to a privileged exception. 83 * If we are using SW PAN, set the DACR user domain to no access
|
/linux-5.10/arch/parisc/kernel/ |
D | traps.c | 1 // SPDX-License-Identifier: GPL-2.0 49 #include "../math-emu/math-emu.h" /* for handle_fpe() */ 56 unsigned long mask = 1UL << (nbits - 1); in printbinary() 71 #define FFMT "%016llx" /* fpregs are 64-bit always */ 74 printk("%s%s%02d-%02d " fmt " " fmt " " fmt " " fmt "\n", \ 85 printbinary(buf, regs->gr[0], 32); in print_gr() 89 PRINTREGS(level, regs->gr, "r", RFMT, i); in print_gr() 96 struct { u32 sw[2]; } s; in print_fr() member 101 * The fldd is used to restore the T-bit if there was one, as the in print_fr() 103 * PA2.0 book says "thou shall not use fstw on FPSR/FPERs" - T-Bone */ in print_fr() [all …]
|
/linux-5.10/Documentation/devicetree/bindings/usb/ |
D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: list of clock names. Ideally should be "ref", 12 - clocks: list of phandle and clock specifier pairs corresponding to 13 entries in the clock-names property. 15 Exception for clocks: 16 clocks are optional if the parent node (i.e. glue-layer) is compatible to 18 "cavium,octeon-7130-usb-uctl" [all …]
|
/linux-5.10/arch/x86/kernel/cpu/mce/ |
D | inject.c | 1 // SPDX-License-Identifier: GPL-2.0-only 15 * Copyright (c) 2010-17: Borislav Petkov <bp@alien8.de> 46 SW_INJ = 0, /* SW injection, simply decode the error */ 54 [SW_INJ] = "sw", 69 m->reg = val; \ 83 *val = m->reg; \ 101 m->cpuvendor = boot_cpu_data.x86_vendor; in setup_inj_struct() 102 m->time = ktime_get_real_seconds(); in setup_inj_struct() 103 m->cpuid = cpuid_eax(1); in setup_inj_struct() 104 m->microcode = boot_cpu_data.microcode; in setup_inj_struct() [all …]
|
/linux-5.10/arch/alpha/kernel/ |
D | signal.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * 1997-11-02 Modified for POSIX.1b signals by Richard Henderson 69 __get_user(new_ka.sa.sa_handler, &act->sa_handler) || in SYSCALL_DEFINE3() 70 __get_user(new_ka.sa.sa_flags, &act->sa_flags) || in SYSCALL_DEFINE3() 71 __get_user(mask, &act->sa_mask)) in SYSCALL_DEFINE3() 72 return -EFAULT; in SYSCALL_DEFINE3() 81 __put_user(old_ka.sa.sa_handler, &oact->sa_handler) || in SYSCALL_DEFINE3() 82 __put_user(old_ka.sa.sa_flags, &oact->sa_flags) || in SYSCALL_DEFINE3() 83 __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask)) in SYSCALL_DEFINE3() 84 return -EFAULT; in SYSCALL_DEFINE3() [all …]
|
/linux-5.10/arch/s390/include/asm/ |
D | pgtable.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 9 * Derived from "include/asm-i386/pgtable.h" 17 #include <linux/page-flags.h> 18 #include <linux/radix-tree.h> 54 * for zero-mapped memory areas etc.. 90 #define VMALLOC_DEFAULT_SIZE ((128UL << 30) - MODULES_LEN) 118 * I Page-Invalid Bit: Page is not available for address-translation 119 * P Page-Protection Bit: Store access not possible for page 120 * C Change-bit override: HW is not required to set change bit 123 * | P-table origin | TT [all …]
|
/linux-5.10/arch/xtensa/variants/dc232b/include/variant/ |
D | core.h | 8 * Copyright (c) 1999-2007 Tensilica Inc. 25 /*---------------------------------------------------------------------- 27 ----------------------------------------------------------------------*/ 29 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 35 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 36 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 68 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 75 /*---------------------------------------------------------------------- 77 ----------------------------------------------------------------------*/ [all …]
|