mips/kernel/genex.S

6  * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
28  * General exception vector for all other CPUs.
31  * to fit into space reserved for the exception handler.
47  * General exception handler for CPUs with virtual coherency exception.
50  * exception) bytes to fit into space reserved for the exception handler.
75 	 * c0_badvaddr because after return from this exception handler the
76 	 * load / store will be re-executed.
80 	li	k1, -4					# Is this ...
89 	sw	k1, (k0)
100 	sw	k1, (k0)
212 	PTR_LI	t1, ~(_THREAD_SIZE-1)
238  * This is a dedicated interrupt exception vector which reduces the
243  * to fit into space reserved for the exception handler.
250  * EJTAG debug exception handler.
251  * The EJTAG debug exception entry point is 0xbfc00480, which
324 	PTR_LI	t1, ~(_THREAD_SIZE-1)
344  * EJTAG debug exception handler.
381 	sw	zero, 0(k0)
430  * NMI debug exception handler for MIPS reference boards.
431  * The NMI debug exception entry point is 0xbfc00000, which
449 	 * Clear ERL - restore segment mapping
450 	 * Clear BEV - required for page fault exception handler to work
505 	 * register. All GSExc-equipped processors have MIPS32.
514 	.macro	__BUILD_silent exception  argument
531 	.macro	__BUILD_count exception  argument
532 	LONG_L	t0,exception_count_\exception
534 	LONG_S	t0,exception_count_\exception
535 	.comm	exception_count\exception, 8, 8
538 	.macro	__BUILD_HANDLER exception handler clear verbose ext
540 	NESTED(handle_\exception, PT_SIZE, sp)
544 	FEXPORT(handle_\exception\ext)
547 	__BUILD_\verbose \exception
551 	END(handle_\exception)
554 	.macro	BUILD_HANDLER exception handler clear verbose
555 	__BUILD_HANDLER \exception \handler \clear \verbose _int