Lines Matching +full:sw +full:- +full:exception
1 # SPDX-License-Identifier: GPL-2.0-only
17 fpu exception handler.
40 possibly significant due to additional FPU exception.
50 A set of Zero-Overhead Loop mechanism is provided to reduce the
51 instruction fetch and execution overhead of loop-control instructions.
102 prompt "Paging -- page size "
111 bool "Disable I-Cache"
117 bool "Disable D-Cache"
123 bool "Force write through D-cache"
133 Say Y here to enable write-back memory with no-write-allocation policy.
136 bool "Kernel support unaligned access handling by sw"
142 address divisible by 4. On 32-bit Andes processors, these non-aligned
144 here, which has a severe performance impact. With an IP-only
152 Andes processors load/store world/half-word instructions can access
154 Check exceptions. With an IP-only configuration it is safe to say N,