1 // SPDX-License-Identifier: GPL-2.0-only
15  * Copyright (c) 2010-17:  Borislav Petkov <bp@alien8.de>
46 	SW_INJ = 0,	/* SW injection, simply decode the error */
54 	[SW_INJ] = "sw",
69 	m->reg = val;							\
83 	*val = m->reg;							\
101 	m->cpuvendor = boot_cpu_data.x86_vendor;  in setup_inj_struct()
102 	m->time	     = ktime_get_real_seconds();  in setup_inj_struct()
103 	m->cpuid     = cpuid_eax(1);  in setup_inj_struct()
104 	m->microcode = boot_cpu_data.microcode;  in setup_inj_struct()
110 	struct mce *i = &per_cpu(injectm, m->extcpu);  in inject_mce()
113 	i->finished = 0;  in inject_mce()
115 	m->finished = 0;  in inject_mce()
117 	i->extcpu = m->extcpu;  in inject_mce()
123 	i->finished = 1;  in inject_mce()
135 	m->finished = 0;  in raise_poll()
145 		regs.ip = m->ip;  in raise_exception()
146 		regs.cs = m->cs;  in raise_exception()
149 	/* do_machine_check() expects interrupts disabled -- at least */  in raise_exception()
153 	m->finished = 0;  in raise_exception()
166 	if (m->inject_flags & MCJ_EXCEPTION)  in mce_raise_notify()
168 	else if (m->status)  in mce_raise_notify()
179 			m->inject_flags & MCJ_EXCEPTION) {  in mce_irq_ipi()
189 	int context = MCJ_CTX(m->inject_flags);  in raise_local()
191 	int cpu = m->extcpu;  in raise_local()
193 	if (m->inject_flags & MCJ_EXCEPTION) {  in raise_local()
194 		pr_info("Triggering MCE exception on CPU %d\n", cpu);  in raise_local()
208 			ret = -EINVAL;  in raise_local()
210 		pr_info("MCE exception done on CPU %d\n", cpu);  in raise_local()
211 	} else if (m->status) {  in raise_local()
217 		m->finished = 0;  in raise_local()
224 	int context = MCJ_CTX(m->inject_flags);  in raise_mce()
231 	if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) {  in raise_mce()
240 			if (!mcpu->finished ||  in raise_mce()
241 			    MCJ_CTX(mcpu->inject_flags) != MCJ_CTX_RANDOM)  in raise_mce()
245 			if (m->inject_flags & MCJ_IRQ_BROADCAST) {  in raise_mce()
254 			} else if (m->inject_flags & MCJ_NMI_BROADCAST)  in raise_mce()
255 				apic->send_IPI_mask(mce_inject_cpumask,  in raise_mce()
330 	return -EINVAL;  in __set_inj()
351 		return -EINVAL;  in flags_write()
354 		return -EFAULT;  in flags_write()
356 	buf[cnt - 1] = 0;  in flags_write()
389 		return -EINVAL;  in inj_extcpu_set()
391 	m->extcpu = val;  in inj_extcpu_set()
417 	cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket();  in get_nbc_for_node()
433 	F3 = nb->misc;  in toggle_nb_mca_mst_cpu()
440 		       __func__, PCI_FUNC(F3->devfn), NBCFG);  in toggle_nb_mca_mst_cpu()
454 		       __func__, PCI_FUNC(F3->devfn), NBCFG);  in toggle_nb_mca_mst_cpu()
509 	 * - MCx_STATUS[Deferred]: make sure it is a deferred error  in do_inject()
510 	 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC  in do_inject()
567 	/* Get bank count on target CPU so we can handle non-uniform values. */  in inj_bank_set()
568 	rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);  in inj_bank_set()
572 		pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu);  in inj_bank_set()
573 		return -EINVAL;  in inj_bank_set()
576 	m->bank = val;  in inj_bank_set()
612 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
613 "\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
621 "\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
623 "\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
627 "\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
630 "\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
665 	dfs_inj = debugfs_create_dir("mce-inject", NULL);  in debugfs_init()
675 		return -ENOMEM;  in inject_init()