Lines Matching +full:sw +full:- +full:exception
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009
15 #include <asm/asm-offsets.h>
17 #include <asm/exception-64e.h>
18 #include <asm/ppc-opcode.h>
21 #include <asm/feature-fixups.h>
36 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not
99 /* We pre-test some combination of permissions to avoid double
120 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
121 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
123 rlwinm r10,r11,32-19,27,27
124 rlwimi r10,r11,32-16,19,19
133 * This is the guts of the TLB miss handler for bolted-linear.
143 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
159 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
165 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
171 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
179 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
180 bne- tlb_miss_fault_bolted
186 * - PID already updated by caller if necessary
187 * - TSIZE need change if !base page size, not
194 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
195 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
198 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
200 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
238 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
240 bne- itlb_miss_fault_bolted
259 * No HES or NV hint on TLB1, so we need to do software round-robin
261 * with MAS-damage caused by tlbsx
309 crclr cr1*4+eq /* set cr1.eq = 0 for non-recursive */
330 * Erratum A-008139 says that we can't use tlbwe to change
348 rlwinm r10,r10,0,0x80000fff /* tgs,tlpid -> sgs,slpid */
353 rlwinm r15,r10,0,0x3fff0000 /* tid -> spid */
354 rlwimi r15,r10,20,0x00000003 /* ind,ts -> sind,sas */
388 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
389 bne- tlb_miss_fault_e6500
391 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
394 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
397 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
403 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
415 * MAS 0 : ESEL needs to be filled by software round-robin
417 * - PID already updated by caller if necessary
418 * - TSIZE for now is base ind page size always
419 * - TID already cleared if necessary
420 * MAS 2 : Default not 2M-aligned, need to be redone
427 clrrdi r15,r16,21 /* make EA 2M-aligned */
468 * MAS 0 : ESEL needs to be filled by software round-robin
469 * - can be handled by indirect code
471 * MAS 2,3+7: Needs to be redone similar to non-tablewalk handler
480 li r10,-0x400
483 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
484 rlwimi r10,r14,32-19,27,31 /* Insert WIMGE */
486 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
489 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
491 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
539 beq tlb_load_linear /* yes -> go to linear map load */
547 bne- virt_page_table_tlb_miss
560 /* We pre-test some combination of permissions to avoid double
577 rlwimi r11,r14,32-19,27,27
578 rlwimi r11,r14,32-16,19,19
600 * info by writing a crazy value in ESR in our exception frame
602 li r14,-1 /* store to exception frame is done later */
606 * not re-enter. We could indeed optimize and also not save SRR0/1
613 beq tlb_load_linear /* yes -> go to linear map load */
621 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
638 * This is the guts of the first-level TLB miss handler for direct
645 * r12 = TLB exception frame in PACA
652 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
659 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
678 bne- normal_tlb_miss_access_fault
684 * - PID already updated by caller if necessary
685 * - TSIZE need change if !base page size, not
693 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
697 rldicl r11,r14,64-8,64-8
699 beq- 1f
706 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
708 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
709 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
711 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
750 * This is the guts of the second-level TLB miss handler for direct
757 * r12 = TLB exception frame in PACA
762 * with the current scheme when using SW load.
764 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
766 * It can be re-entered by the linear mapping miss handler. However, to
779 * pgdir in the PACA :-).
801 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
802 bne- virt_page_table_tlb_miss_fault
807 beq- virt_page_table_tlb_miss_fault
810 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
817 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
824 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
831 * a 4K or 64K page from r16 -> r15.
837 * - PID already updated by caller if necessary
838 * - TSIZE for now is base page size always
845 ori r10,r11,1 /* Or-in SR */
865 * ITLB miss handler to also store SRR0 in the exception frame
870 * are not a level 0 exception (we interrupted the TLB miss) we
871 * offset the return address by -4 in order to replay the tlbsrx
876 bne- 1f
878 addi r10,r11,-4
892 * always called as a second level tlb miss for SW load or as a first
894 * relevant information in the first exception frame in the PACA.
907 bne- virt_page_table_tlb_miss_whacko_fault
914 cmpdi cr0,r16,-1
951 beq tlb_load_linear /* yes -> go to linear map load */
982 li r14,-1 /* store to exception frame is done later */
986 * not re-enter. We could indeed optimize and also not save SRR0/1
993 beq tlb_load_linear /* yes -> go to linear map load */
1015 * This is the guts of the second-level TLB miss handler for direct
1022 * r12 = TLB exception frame in PACA
1026 * It can be re-entered by the linear mapping miss handler. However, to
1041 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
1042 bne- htw_tlb_miss_fault
1046 beq- htw_tlb_miss_fault
1049 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
1056 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
1063 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
1079 rlwimi r15,r16,32-9,20,20
1084 * - PID already updated by caller if necessary
1085 * - TSIZE for now is base ind page size always
1111 * though because r14 would contain -1
1113 cmpdi cr0,r14,-1
1129 * r14 = ESR (data) or -1 (instruction)
1131 * r12 = TLB exception frame in PACA
1135 * In addition we know that we will not re-enter, so in theory, we could
1199 cmpdi cr0,r14,-1