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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos9810-pinctrl.dtsi16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 interrupt-parent = <&gic>;
34 #interrupt-cells = <2>;
41 interrupt-controller;
42 interrupt-parent = <&gic>;
51 #interrupt-cells = <2>;
58 interrupt-controller;
59 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,rzg2l-irqc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
35 '#interrupt-cells':
37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
44 interrupt-controller: true
52 - description: NMI interrupt
53 - description: IRQ0 interrupt
[all …]
H A Dfsl,imx8qxp-dc-intc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
20 allowing it to use a global interrupt controller instead.
22 Each interrupt can be protected against SW running in user mode. In that case,
23 only privileged AHB access can control the interrupt status.
38 interrupt-controller: true
40 "#interrupt-cells":
45 - description: store9 shadow load interrupt(blit engine)
[all …]
H A Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
[all …]
H A Dsamsung,exynos4210-combiner.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
[all …]
H A Dbrcm,bcm7120-l2-intc.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
30 - not all bits within the interrupt controller actually map to an interrupt
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
[all …]
H A Driscv,aplic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
19 interrupt sources connect to the root APLIC domain and a parent APLIC
20 domain can delegate interrupt sources to it's child APLIC domains. There
24 - $ref: /schemas/interrupt-controller.yaml#
37 interrupt-controller: true
39 "#interrupt-cells":
53 message signaled interrupt controller (IMSIC). If both "msi-parent" and
[all …]
/linux/drivers/net/ipa/
H A Dipa_interrupt.c9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
22 #include <linux/interrupt.h>
36 * struct ipa_interrupt - IPA interrupt information
40 * @suspend_enabled: Bitmap of endpoints with the SUSPEND interrupt enabled
49 /* Clear the suspend interrupt for all endpoints that signaled it */
50 static void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) in ipa_interrupt_suspend_clear_all() argument
52 struct ipa *ipa = interrupt->ipa; in ipa_interrupt_suspend_clear_all()
64 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ in ipa_interrupt_suspend_clear_all()
73 /* Process a particular interrupt type that has been received */
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/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
[all …]
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath11k.yaml32 interrupt-names:
111 - description: misc-pulse1 interrupt events
112 - description: misc-latch interrupt events
113 - description: sw exception interrupt events
114 - description: watchdog interrupt events
115 - description: interrupt event for ring CE0
116 - description: interrupt event for ring CE1
117 - description: interrupt event for ring CE2
118 - description: interrupt event for ring CE3
119 - description: interrupt event for ring CE4
[all …]
H A Dqcom,ipq5332-wifi.yaml34 - description: Fatal interrupt
35 - description: Ready interrupt
36 - description: Spawn acknowledge interrupt
37 - description: Stop acknowledge interrupt
38 - description: misc-pulse1 interrupt events
39 - description: misc-latch interrupt events
40 - description: sw exception interrupt events
41 - description: interrupt event for ring CE0
42 - description: interrupt event for ring CE1
43 - description: interrupt event for ring CE2
[all …]
/linux/arch/powerpc/boot/dts/
H A Dfsp2.dts64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
/linux/sound/soc/sdca/
H A Dsdca_fdl.c75 * @info: Pointer to the SDCA interrupt info for this device.
92 struct sdca_interrupt *interrupt = &info->irqs[j]; in sdca_fdl_sync() local
96 if (interrupt->function != function || in sdca_fdl_sync()
97 !interrupt->entity || !interrupt->control || in sdca_fdl_sync()
98 interrupt->entity->type != SDCA_ENTITY_TYPE_XU || in sdca_fdl_sync()
99 interrupt->control->sel != SDCA_CTL_XU_FDL_CURRENTOWNER) in sdca_fdl_sync()
102 fdl_state = interrupt->priv; in sdca_fdl_sync()
135 struct sdca_interrupt *interrupt = &info->irqs[j]; in sdca_fdl_sync() local
138 if (interrupt in sdca_fdl_sync()
198 fdl_load_file(struct sdca_interrupt * interrupt,struct sdca_fdl_set * set,int file_index) fdl_load_file() argument
280 fdl_get_set(struct sdca_interrupt * interrupt) fdl_get_set() argument
313 fdl_end(struct sdca_interrupt * interrupt) fdl_end() argument
332 struct sdca_interrupt *interrupt = fdl_state->interrupt; sdca_fdl_timeout_work() local
343 fdl_status_process(struct sdca_interrupt * interrupt,unsigned int status) fdl_status_process() argument
401 sdca_fdl_process(struct sdca_interrupt * interrupt) sdca_fdl_process() argument
485 sdca_fdl_alloc_state(struct sdca_interrupt * interrupt) sdca_fdl_alloc_state() argument
[all...]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7358.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7360.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
H A Dbcm7346.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7362.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7425.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
H A Dbcm7435.dtsi42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dls7a-pch.dtsi13 pic: interrupt-controller@10000000 {
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
19 #interrupt-cells = <2>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
89 interrupt-parent = <&pic>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi8 #include <dt-bindings/interrupt-controller/irq.h>
41 cpuintc: interrupt-controller {
42 compatible = "loongson,cpu-interrupt-controller";
43 #interrupt-cells = <1>;
44 interrupt-controller;
96 interrupt-parent = <&eiointc>;
119 interrupt-parent = <&liointc>;
124 liointc: interrupt-controller@1fe01400 {
128 interrupt-controller;
130 #interrupt-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dhisilicon,hip06-sec.yaml41 - description: SEC unit error queue interrupt
42 - description: Completion interrupt for queue 0
43 - description: Error interrupt for queue 0
44 - description: Completion interrupt for queue 1
45 - description: Error interrupt for queue 1
46 - description: Completion interrupt for queue 2
47 - description: Error interrupt for queue 2
48 - description: Completion interrupt for queue 3
49 - description: Error interrupt for queue 3
50 - description: Completion interrupt for queue 4
[all …]
/linux/arch/arm64/boot/dts/exynos/axis/
H A Dartpec8-pinctrl.dtsi17 interrupt-controller;
18 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
31 interrupt-controller;
32 #interrupt-cells = <2>;
38 interrupt-controller;
39 #interrupt-cells = <2>;
45 interrupt-controller;
46 #interrupt-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi122 interrupt-names = "intx";
124 #interrupt-cells = <1>;
128 interrupt-map-mask = <0 0 0 7>;
129 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
138 pcie1_intc: interrupt-controller {
139 interrupt-controller;
140 #interrupt-cells = <1>;
150 interrupt-names = "intx";
152 #interrupt-cells = <1>;
156 interrupt-map-mask = <0 0 0 7>;
[all …]

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