Merge branch 'arm/queue' into 'master'

arm/arm64: EFI support, arm64 backtrace support, PMU test improvements, and more

See merge request kvm-unit-tests/kvm-unit-tests!43

arm64: Add support for timer initialization through ACPI

For systems with ACPI support, we can discover timers through the ACPI
GTDT table. This change implements the code to discover timers through

arm64: Add support for timer initialization through ACPI

For systems with ACPI support, we can discover timers through the ACPI
GTDT table. This change implements the code to discover timers through
the GTDT and adds ACPI support in timer_save_state. This change
retains the default behavior; we check if a valid DT is provided, if
not, we try to discover timers using ACPI.

Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'arm/queue' into 'master'

arm cleanups

See merge request kvm-unit-tests/kvm-unit-tests!41

arm64: timer: Use gic_enable/disable_irq() macro in timer test

Use gic_enable/disable_irq() to clean up the code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.au

arm64: timer: Use gic_enable/disable_irq() macro in timer test

Use gic_enable/disable_irq() to clean up the code.

Signed-off-by: Shaoqin Huang <shahuang@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>

show more ...

Merge branch 'arm/queue' into 'master'

arm64: Merge arm/queue

See merge request kvm-unit-tests/kvm-unit-tests!23

arm: timer: Take into account other wake-up events for the TVAL test

The TVAL test programs the timer to fire into the future, waits for an
interrupt using the WFI instruction, and when the instruct

arm: timer: Take into account other wake-up events for the TVAL test

The TVAL test programs the timer to fire into the future, waits for an
interrupt using the WFI instruction, and when the instruction completes it
checks that the timer interrupt has fired. According to ARM DDI 0487G.a
there are other wake-up events that can cause the WFI to complete (listed
on page D1-2520), among them interrupts routed to a higher exception level,
where the hypervisor is running (if running under virtualization) or
firmware (if running on baremetal).

In practice, this is unlikely to have caused a false test failure, because
for a GICv3 (which the author assumes is a lot more common than a GICv4+)
the WFI is trapped by KVM and the VCPU thread is resumed only after the
timer asserts the interrupt, as the test expects.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Message-Id: <20211207154641.87740-5-alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm: timer: Test CVAL before interrupt pending state

The timer pending test uses CVAL to trigger changes in the timer interrupt
state. Move the CVAL test before the pending test to make sure that wr

arm: timer: Test CVAL before interrupt pending state

The timer pending test uses CVAL to trigger changes in the timer interrupt
state. Move the CVAL test before the pending test to make sure that writes
to the CVAL register have an effect on the timer internal state before
using the register for other tests.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Message-Id: <20211207154641.87740-4-alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm: timer: Move the different tests into their own functions

At the moment, the timer test is one big function that checks different
aspects of the timer implementation, and it's not immediately ob

arm: timer: Move the different tests into their own functions

At the moment, the timer test is one big function that checks different
aspects of the timer implementation, and it's not immediately obvious if a
check depends on a state from a previous test, making understanding the
code more difficult than necessary.

Move the checks into logically distinct functions and leave the timer in a
known state before proceeding to the next test to make the code easier to
understand, maintain and extend.

The timer interrupt is now enabled at the GIC level in test_init() to break
the dependency that the tests have on the timer pending test running first.

There should be no functional change as a result of this patch.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Message-Id: <20211207154641.87740-3-alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm: timer: Fix TVAL comparison for timer condition met

ARM DDI 0487G.a states on page D13-4180 that, when the virtual timer is
enabled, the timer condition is met when CNTVCT_EL0 - CNTV_CVAL_EL0 >=

arm: timer: Fix TVAL comparison for timer condition met

ARM DDI 0487G.a states on page D13-4180 that, when the virtual timer is
enabled, the timer condition is met when CNTVCT_EL0 - CNTV_CVAL_EL0 >= 0.
Multiplying both sides of the inequality by -1, we get the equivalent
condition CNTV_CVAL_EL0 - CNTVCT_EL0 <= 0 for when the timer should fire.

On the same page, it states that a read of the CNTV_TVAL_EL0 register
returns CNTV_CVAL_EL0 - CNTVCT_EL0 if the virtual timer is enabled.
Putting the two together, the timer condition is met when the value of the
TVAL register is less than or *equal* to 0.

Same rules apply for the physical timer.

Fix the check for the timer expiring by treating a TVAL value equal to zero
as a valid condition for the timer to fire.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Message-Id: <20211207154641.87740-2-alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

Use report_fail(...) instead of report(0/false, ...)

Whitespace is kept consistent with the rest of the file.

Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Reviewed-by: Thomas Huth <

Use report_fail(...) instead of report(0/false, ...)

Whitespace is kept consistent with the rest of the file.

Signed-off-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-Id: <20211005090921.1816373-5-scgl@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

arm/arm64: timer: Extract irqs at setup time

The timer can be useful for other tests besides the timer test.
Extract the DT parsing of the irqs out of the timer test into
setup and provide them alon

arm/arm64: timer: Extract irqs at setup time

The timer can be useful for other tests besides the timer test.
Extract the DT parsing of the irqs out of the timer test into
setup and provide them along with some defines in a new timer.h
file.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

arm/arm64: timer: Extract irqs at setup time

The timer can be useful for other tests besides the timer test.
Extract the DT parsing of the irqs out of the timer test into
setup and provide them alon

arm/arm64: timer: Extract irqs at setup time

The timer can be useful for other tests besides the timer test.
Extract the DT parsing of the irqs out of the timer test into
setup and provide them along with some defines in a new timer.h
file.

Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Speed up gic-timer-state check

Let's bail out of the wait loop if we see the expected state
to save over six seconds of run time. Make sure we wait a bit
before reading the registers a

arm64: timer: Speed up gic-timer-state check

Let's bail out of the wait loop if we see the expected state
to save over six seconds of run time. Make sure we wait a bit
before reading the registers and double check again after,
though, to somewhat mitigate the chance of seeing the expected
state by accident.

We also take this opportunity to push more IRQ state code to
the library.

Cc: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Tested-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Use existing helpers to access counter/timers

We already have some good helpers to access the counter and timer
registers. Use them to avoid open coding the accessors again.

Signed-o

arm64: timer: Use existing helpers to access counter/timers

We already have some good helpers to access the counter and timer
registers. Use them to avoid open coding the accessors again.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Use the proper RDist register name in GICv3

We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in
SGI_base frame of the redistribitor) to get the active/pending state
of t

arm64: timer: Use the proper RDist register name in GICv3

We're actually going to read GICR_ISACTIVER0 and GICR_ISPENDR0 (in
SGI_base frame of the redistribitor) to get the active/pending state
of the timer interrupt. Fix this typo.

And since they have the same value, there's no functional change.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm/arm64: gic: Move gic_state enumeration to asm/gic.h

The status of each interrupt are defined by the GIC architecture and
maintained by GIC hardware. They're not specified to the timer HW.
Let's

arm/arm64: gic: Move gic_state enumeration to asm/gic.h

The status of each interrupt are defined by the GIC architecture and
maintained by GIC hardware. They're not specified to the timer HW.
Let's move this software enumeration to a more proper place.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Test behavior when timer disabled or masked

When the timer is disabled (the *_CTL_EL0.ENABLE bit is clear) or the
timer interrupt is masked at the timer level (the *_CTL_EL0.IMASK bit

arm64: timer: Test behavior when timer disabled or masked

When the timer is disabled (the *_CTL_EL0.ENABLE bit is clear) or the
timer interrupt is masked at the timer level (the *_CTL_EL0.IMASK bit is
set), timer interrupts must not be pending or asserted by the VGIC.
However, only when the timer interrupt is masked, we can still check
that the timer condition is met by reading the *_CTL_EL0.ISTATUS bit.

This test was used to discover a bug and test the fix introduced by KVM
commit 16e604a437c8 ("KVM: arm/arm64: vgic: Reevaluate level sensitive
interrupts on enable").

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Check the timer interrupt state

We check that the interrupt is pending (or not) at the GIC level, but we
don't check if the timer is asserting it (or not). Let's make sure we don't
run

arm64: timer: Check the timer interrupt state

We check that the interrupt is pending (or not) at the GIC level, but we
don't check if the timer is asserting it (or not). Let's make sure we don't
run into a strange situation where the two devices' states aren't
synchronized.

Coincidently, the "interrupt signal no longer pending" test fails for
non-emulated timers (i.e, the virtual timer on a non-vhe host) if the
host kernel doesn't have patch 16e604a437c89 ("KVM: arm/arm64: vgic:
Reevaluate level sensitive interrupts on enable").

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Wait for the GIC to sample timer interrupt state

There is a delay between the timer asserting the interrupt and the GIC
sampling the interrupt state. Let's take that into account when

arm64: timer: Wait for the GIC to sample timer interrupt state

There is a delay between the timer asserting the interrupt and the GIC
sampling the interrupt state. Let's take that into account when we are
checking if the timer interrupt is pending (or not) at the GIC level.

An interrupt can be pending or active and pending [1,2]. Let's be precise
and check that the interrupt is actually pending, not active and pending.

[1] ARM IHI 0048B.b, section 1.4.1
[2] ARM IHI 0069E, section 1.2.2

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: EOIR the interrupt after masking the timer

Writing to the EOIR register before masking the HW mapped timer
interrupt can cause taking another timer interrupt immediately after
exceptio

arm64: timer: EOIR the interrupt after masking the timer

Writing to the EOIR register before masking the HW mapped timer
interrupt can cause taking another timer interrupt immediately after
exception return. This doesn't happen all the time, because KVM
reevaluates the state of pending HW mapped level sensitive interrupts on
each guest exit. If the second interrupt is pending and a guest exit
occurs after masking the timer interrupt and before the ERET (which
restores PSTATE.I), then KVM removes it.

Move the write after the IMASK bit has been set to prevent this from
happening.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Make irq_received volatile

The irq_received field is modified by the interrupt handler. Make it
volatile so that the compiler doesn't reorder accesses with regard to
the instruction th

arm64: timer: Make irq_received volatile

The irq_received field is modified by the interrupt handler. Make it
volatile so that the compiler doesn't reorder accesses with regard to
the instruction that will be causing the interrupt.

Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Add ISB before reading the counter value

Reads of the physical counter and the virtual counter registers "can occur
speculatively and out of order relative to other instructions execut

arm64: timer: Add ISB before reading the counter value

Reads of the physical counter and the virtual counter registers "can occur
speculatively and out of order relative to other instructions executed on
the same PE" [1, 2].

There is no theoretical limit to the number of instructions that the CPU
can reorder and we use the counter value to program the timer to fire in
the future. Add an ISB before reading the counter to make sure the read
instruction is not reordered too long in the past with regard to the
instruction that programs the timer alarm, thus causing the timer to fire
unexpectedly. This matches what Linux does (see
arch/arm64/include/asm/arch_timer.h).

Because we use the counter value to program the timer, we create a register
dependency [3] between the value that we read and the value that we write to
CVAL and thus we don't need a barrier after the read. Linux does things
differently because the read needs to be ordered with regard to a memory
load (more information in commit 75a19a0202db ("arm64: arch_timer: Ensure
counter register reads occur with seqlock held")).

This also matches what we already do in get_cntvct from
lib/arm{,64}/asm/processor.h.

[1] ARM DDI 0487E.a, section D11.2.1
[2] ARM DDI 0487E.a, section D11.2.2
[3] ARM DDI 0486E.a, section B2.3.2

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

arm64: timer: Add ISB after register writes

From ARM DDI 0487E.a glossary, the section "Context synchronization
event":

"All direct and indirect writes to System registers that are made before
the

arm64: timer: Add ISB after register writes

From ARM DDI 0487E.a glossary, the section "Context synchronization
event":

"All direct and indirect writes to System registers that are made before
the Context synchronization event affect any instruction, including a
direct read, that appears in program order after the instruction causing
the Context synchronization event."

The ISB instruction is a context synchronization event [1]. Add an ISB
after all register writes, to make sure that the writes have been
completed when we try to test their effects.

[1] ARM DDI 0487E.a, section C6.2.96

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...

Merge branch 'arm/queue' of https://github.com/rhdrjones/kvm-unit-tests into HEAD

arm64: timer: Write to ICENABLER to disable timer IRQ

According the Generic Interrupt Controller versions 2, 3 and 4 architecture
specifications, a write of 0 to the GIC{D,R}_ISENABLER{,0} registers

arm64: timer: Write to ICENABLER to disable timer IRQ

According the Generic Interrupt Controller versions 2, 3 and 4 architecture
specifications, a write of 0 to the GIC{D,R}_ISENABLER{,0} registers is
ignored; this is also how KVM emulates the corresponding register. Write
instead to the ICENABLER register when disabling the timer interrupt.

Note that fortunately for us, the timer test was still working as intended
because KVM does the sensible thing and all interrupts are disabled by
default when creating a VM.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>

show more ...