1 /* 2 * Timer tests for the ARM virt machine. 3 * 4 * Copyright (C) 2017, Alexander Graf <agraf@suse.de> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. 7 */ 8 #include <libcflat.h> 9 #include <devicetree.h> 10 #include <errata.h> 11 #include <asm/processor.h> 12 #include <asm/gic.h> 13 #include <asm/io.h> 14 15 #define ARCH_TIMER_CTL_ENABLE (1 << 0) 16 #define ARCH_TIMER_CTL_IMASK (1 << 1) 17 #define ARCH_TIMER_CTL_ISTATUS (1 << 2) 18 19 static void *gic_ispendr; 20 static void *gic_isenabler; 21 static void *gic_icenabler; 22 23 static bool ptimer_unsupported; 24 25 static void ptimer_unsupported_handler(struct pt_regs *regs, unsigned int esr) 26 { 27 ptimer_unsupported = true; 28 regs->pc += 4; 29 } 30 31 static u64 read_vtimer_counter(void) 32 { 33 isb(); 34 return read_sysreg(cntvct_el0); 35 } 36 37 static u64 read_vtimer_cval(void) 38 { 39 return read_sysreg(cntv_cval_el0); 40 } 41 42 static void write_vtimer_cval(u64 val) 43 { 44 write_sysreg(val, cntv_cval_el0); 45 isb(); 46 } 47 48 static s32 read_vtimer_tval(void) 49 { 50 return read_sysreg(cntv_tval_el0); 51 } 52 53 static void write_vtimer_tval(s32 val) 54 { 55 write_sysreg(val, cntv_tval_el0); 56 isb(); 57 } 58 59 static u64 read_vtimer_ctl(void) 60 { 61 return read_sysreg(cntv_ctl_el0); 62 } 63 64 static void write_vtimer_ctl(u64 val) 65 { 66 write_sysreg(val, cntv_ctl_el0); 67 isb(); 68 } 69 70 static u64 read_ptimer_counter(void) 71 { 72 isb(); 73 return read_sysreg(cntpct_el0); 74 } 75 76 static u64 read_ptimer_cval(void) 77 { 78 return read_sysreg(cntp_cval_el0); 79 } 80 81 static void write_ptimer_cval(u64 val) 82 { 83 write_sysreg(val, cntp_cval_el0); 84 isb(); 85 } 86 87 static s32 read_ptimer_tval(void) 88 { 89 return read_sysreg(cntp_tval_el0); 90 } 91 92 static void write_ptimer_tval(s32 val) 93 { 94 write_sysreg(val, cntp_tval_el0); 95 isb(); 96 } 97 98 static u64 read_ptimer_ctl(void) 99 { 100 return read_sysreg(cntp_ctl_el0); 101 } 102 103 static void write_ptimer_ctl(u64 val) 104 { 105 write_sysreg(val, cntp_ctl_el0); 106 isb(); 107 } 108 109 struct timer_info { 110 u32 irq; 111 u32 irq_flags; 112 volatile bool irq_received; 113 u64 (*read_counter)(void); 114 u64 (*read_cval)(void); 115 void (*write_cval)(u64); 116 s32 (*read_tval)(void); 117 void (*write_tval)(s32); 118 u64 (*read_ctl)(void); 119 void (*write_ctl)(u64); 120 }; 121 122 static struct timer_info vtimer_info = { 123 .irq_received = false, 124 .read_counter = read_vtimer_counter, 125 .read_cval = read_vtimer_cval, 126 .write_cval = write_vtimer_cval, 127 .read_tval = read_vtimer_tval, 128 .write_tval = write_vtimer_tval, 129 .read_ctl = read_vtimer_ctl, 130 .write_ctl = write_vtimer_ctl, 131 }; 132 133 static struct timer_info ptimer_info = { 134 .irq_received = false, 135 .read_counter = read_ptimer_counter, 136 .read_cval = read_ptimer_cval, 137 .write_cval = write_ptimer_cval, 138 .read_tval = read_ptimer_tval, 139 .write_tval = write_ptimer_tval, 140 .read_ctl = read_ptimer_ctl, 141 .write_ctl = write_ptimer_ctl, 142 }; 143 144 static void set_timer_irq_enabled(struct timer_info *info, bool enabled) 145 { 146 u32 val = 1 << PPI(info->irq); 147 148 if (enabled) 149 writel(val, gic_isenabler); 150 else 151 writel(val, gic_icenabler); 152 } 153 154 static void irq_handler(struct pt_regs *regs) 155 { 156 struct timer_info *info; 157 u32 irqstat = gic_read_iar(); 158 u32 irqnr = gic_iar_irqnr(irqstat); 159 160 if (irqnr == PPI(vtimer_info.irq)) { 161 info = &vtimer_info; 162 } else if (irqnr == PPI(ptimer_info.irq)) { 163 info = &ptimer_info; 164 } else { 165 if (irqnr != GICC_INT_SPURIOUS) 166 gic_write_eoir(irqstat); 167 report_info("Unexpected interrupt: %d\n", irqnr); 168 return; 169 } 170 171 info->write_ctl(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE); 172 gic_write_eoir(irqstat); 173 174 info->irq_received = true; 175 } 176 177 static bool gic_timer_pending(struct timer_info *info) 178 { 179 return readl(gic_ispendr) & (1 << PPI(info->irq)); 180 } 181 182 static bool test_cval_10msec(struct timer_info *info) 183 { 184 u64 time_10ms = read_sysreg(cntfrq_el0) / 100; 185 u64 time_1us = time_10ms / 10000; 186 u64 before_timer, after_timer; 187 s64 difference; 188 189 /* Program timer to fire in 10 ms */ 190 before_timer = info->read_counter(); 191 info->write_cval(before_timer + time_10ms); 192 info->write_ctl(ARCH_TIMER_CTL_ENABLE); 193 194 /* Wait for the timer to fire */ 195 while (!(info->read_ctl() & ARCH_TIMER_CTL_ISTATUS)) 196 ; 197 198 /* It fired, check how long it took */ 199 after_timer = info->read_counter(); 200 difference = after_timer - (before_timer + time_10ms); 201 202 report_info("After timer: 0x%016lx", after_timer); 203 report_info("Expected : 0x%016lx", before_timer + time_10ms); 204 report_info("Difference : %ld us", difference / time_1us); 205 206 if (difference < 0) { 207 printf("ISTATUS set too early\n"); 208 return false; 209 } 210 return difference < time_10ms; 211 } 212 213 static void test_timer(struct timer_info *info) 214 { 215 u64 now = info->read_counter(); 216 u64 time_10s = read_sysreg(cntfrq_el0) * 10; 217 u64 later = now + time_10s; 218 s32 left; 219 220 /* We don't want the irq handler to fire because that will change the 221 * timer state and we want to test the timer output signal. We can 222 * still read the pending state even if it's disabled. */ 223 set_timer_irq_enabled(info, false); 224 225 /* Enable the timer, but schedule it for much later */ 226 info->write_cval(later); 227 info->write_ctl(ARCH_TIMER_CTL_ENABLE); 228 report(!gic_timer_pending(info), "not pending before"); 229 230 info->write_cval(now - 1); 231 report(gic_timer_pending(info), "interrupt signal pending"); 232 233 /* Disable the timer again and prepare to take interrupts */ 234 info->write_ctl(0); 235 set_timer_irq_enabled(info, true); 236 report(!gic_timer_pending(info), "interrupt signal no longer pending"); 237 238 report(test_cval_10msec(info), "latency within 10 ms"); 239 report(info->irq_received, "interrupt received"); 240 241 /* Disable the timer again */ 242 info->write_ctl(0); 243 244 /* Test TVAL and IRQ trigger */ 245 info->irq_received = false; 246 info->write_tval(read_sysreg(cntfrq_el0) / 100); /* 10 ms */ 247 local_irq_disable(); 248 info->write_ctl(ARCH_TIMER_CTL_ENABLE); 249 report_info("waiting for interrupt..."); 250 wfi(); 251 local_irq_enable(); 252 left = info->read_tval(); 253 report(info->irq_received, "interrupt received after TVAL/WFI"); 254 report(left < 0, "timer has expired"); 255 report_info("TVAL is %d ticks", left); 256 } 257 258 static void test_vtimer(void) 259 { 260 report_prefix_push("vtimer-busy-loop"); 261 test_timer(&vtimer_info); 262 report_prefix_pop(); 263 } 264 265 static void test_ptimer(void) 266 { 267 if (ptimer_unsupported) 268 return; 269 270 report_prefix_push("ptimer-busy-loop"); 271 test_timer(&ptimer_info); 272 report_prefix_pop(); 273 } 274 275 static void test_init(void) 276 { 277 const struct fdt_property *prop; 278 const void *fdt = dt_fdt(); 279 int node, len; 280 u32 *data; 281 282 node = fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer"); 283 assert(node >= 0); 284 prop = fdt_get_property(fdt, node, "interrupts", &len); 285 assert(prop && len == (4 * 3 * sizeof(u32))); 286 287 data = (u32 *)prop->data; 288 assert(fdt32_to_cpu(data[3]) == 1); 289 ptimer_info.irq = fdt32_to_cpu(data[4]); 290 ptimer_info.irq_flags = fdt32_to_cpu(data[5]); 291 assert(fdt32_to_cpu(data[6]) == 1); 292 vtimer_info.irq = fdt32_to_cpu(data[7]); 293 vtimer_info.irq_flags = fdt32_to_cpu(data[8]); 294 295 install_exception_handler(EL1H_SYNC, ESR_EL1_EC_UNKNOWN, ptimer_unsupported_handler); 296 read_sysreg(cntp_ctl_el0); 297 install_exception_handler(EL1H_SYNC, ESR_EL1_EC_UNKNOWN, NULL); 298 299 if (ptimer_unsupported && !ERRATA(7b6b46311a85)) { 300 report_skip("Skipping ptimer tests. Set ERRATA_7b6b46311a85=y to enable."); 301 } else if (ptimer_unsupported) { 302 report(false, "ptimer: read CNTP_CTL_EL0"); 303 report_info("ptimer: skipping remaining tests"); 304 } 305 306 gic_enable_defaults(); 307 308 switch (gic_version()) { 309 case 2: 310 gic_ispendr = gicv2_dist_base() + GICD_ISPENDR; 311 gic_isenabler = gicv2_dist_base() + GICD_ISENABLER; 312 gic_icenabler = gicv2_dist_base() + GICD_ICENABLER; 313 break; 314 case 3: 315 gic_ispendr = gicv3_sgi_base() + GICD_ISPENDR; 316 gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0; 317 gic_icenabler = gicv3_sgi_base() + GICR_ICENABLER0; 318 break; 319 } 320 321 install_irq_handler(EL1H_IRQ, irq_handler); 322 local_irq_enable(); 323 } 324 325 static void print_timer_info(void) 326 { 327 printf("CNTFRQ_EL0 : 0x%016lx\n", read_sysreg(cntfrq_el0)); 328 329 if (!ptimer_unsupported){ 330 printf("CNTPCT_EL0 : 0x%016lx\n", read_sysreg(cntpct_el0)); 331 printf("CNTP_CTL_EL0 : 0x%016lx\n", read_sysreg(cntp_ctl_el0)); 332 printf("CNTP_CVAL_EL0: 0x%016lx\n", read_sysreg(cntp_cval_el0)); 333 } 334 335 printf("CNTVCT_EL0 : 0x%016lx\n", read_sysreg(cntvct_el0)); 336 printf("CNTV_CTL_EL0 : 0x%016lx\n", read_sysreg(cntv_ctl_el0)); 337 printf("CNTV_CVAL_EL0: 0x%016lx\n", read_sysreg(cntv_cval_el0)); 338 } 339 340 int main(int argc, char **argv) 341 { 342 int i; 343 344 test_init(); 345 346 print_timer_info(); 347 348 if (argc == 1) { 349 test_vtimer(); 350 test_ptimer(); 351 } 352 353 for (i = 1; i < argc; ++i) { 354 if (strcmp(argv[i], "vtimer") == 0) 355 test_vtimer(); 356 if (strcmp(argv[i], "ptimer") == 0) 357 test_ptimer(); 358 } 359 360 return report_summary(); 361 } 362