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/qemu/tests/tcg/arm/system/
H A Dboot.S9 * R0 - semihosting call number
10 * R1 - semihosting parameter
24 .global \name
26 .size \name, . - \name
33 b reset /* reset vector */
57 ite EQ // if-then-else. "EQ" is for if equal, else otherwise
79 * PA[31:20] - Section Base Address
80 * NS[19] - Non-secure bit
81 * 0[18] - Section (1 for Super Section)
82 * nG[17] - Not global bit
[all …]
H A Dtest-armv6m-undef.S2 * Test ARMv6-M UNDEFINED 32-bit instructions
7 * or later. See the COPYING file in the top-level directory.
11 * Test that UNDEFINED 32-bit instructions fault as expected. This is an
12 * interesting test because ARMv6-M shares code with its more fully-featured
16 * The emulator must be invoked with -semihosting so that the test case can
19 * Failures can be debugged with -d in_asm,int,exec,cpu and the
20 * gdbstub (-S -s).
24 .cpu cortex-m0
42 .word exc_reset_thumb /* 1. Reset */
46 .word 0 /* 4-10. Reserved */
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/qemu/hw/openrisc/
H A Dcputimer.c4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
25 #include "system/reset.h"
29 /* Tick Timer global state to allow all cores to be in sync */
40 or1k_timer->ttcr = val; in cpu_openrisc_count_set()
41 or1k_timer->ttcr_offset = val; in cpu_openrisc_count_set()
42 or1k_timer->clk_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in cpu_openrisc_count_set()
47 return or1k_timer->ttcr; in cpu_openrisc_count_get()
55 if (!cpu->env.is_counting) { in cpu_openrisc_count_update()
59 or1k_timer->ttcr = or1k_timer->ttcr_offset + in cpu_openrisc_count_update()
60 DIV_ROUND_UP(now - or1k_timer->clk_offset, TIMER_PERIOD); in cpu_openrisc_count_update()
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/qemu/tests/qtest/
H A Dpflash-cfi02-test.c7 * See the COPYING file in the top-level directory.
16 * all. In particular, we're limited to a 16-bit wide flash device.
20 #define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX)
90 return (uint64_t)-1; in device_mask()
98 if (c->bank_width == 8) { in bank_mask()
99 return (uint64_t)-1; in bank_mask()
101 return (1ULL << (c->bank_width * 8)) - 1ULL; in bank_mask()
110 switch (c->bank_width) { in flash_write()
112 qtest_writeb(c->qtest, addr, data); in flash_write()
115 qtest_writew(c->qtest, addr, data); in flash_write()
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H A Dq35-test.c9 * See the COPYING file in the top-level directory.
15 #include "libqos/pci-pc.h"
16 #include "hw/pci-host/q35.h"
29 * @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes,
88 qts = qtest_init("-M q35"); in test_smram_lock()
108 /* reset */ in test_smram_lock()
133 if (args->esmramc_tseg_sz == MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { in test_tseg_size()
134 qts = qtest_initf("-M q35 -m %uM -global mch.extended-tseg-mbytes=%u", in test_tseg_size()
136 args->extended_tseg_mbytes); in test_tseg_size()
138 qts = qtest_initf("-M q35 -m %uM", TSEG_SIZE_TEST_GUEST_RAM_MBYTES); in test_tseg_size()
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/qemu/include/block/
H A Dblockjob.h2 * Declarations for long-running block device operations
29 #include "qapi/qapi-types-block-core.h"
40 * Long-running operation on a BlockDriverState.
50 * Status that is published by the query-block-jobs QMP API.
63 * RateLimit API is thread-safe.
98 * Global state (GS) API. These functions run under the BQL.
100 * See include/block/block-global-state.h for more information about
171 * Set a rate-limiting parameter for the job; the actual meaning may
201 * @job: The job whose I/O status should be reset.
203 * Reset I/O status on @job and on BlockDriverState objects it uses,
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/qemu/include/hw/ppc/
H A Dopenpic.h18 OPENPIC_OUTPUT_RESET, /* Core reset event */
50 IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
75 bool level:1; /* level-triggered */
92 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
99 uint32_t tccr; /* Global timer current count register */
100 uint32_t tbcr; /* Global timer base count register */
122 /* Count of IRQ sources asserting on non-INT outputs */
150 /* Sub-regions */
153 /* Global registers */
155 uint32_t gcr; /* Global configuration register */
/qemu/hw/misc/
H A Dvmcoreinfo.c6 * Authors: Marc-André Lureau <marcandre.lureau@redhat.com>
9 * See the COPYING file in the top-level directory.
16 #include "system/reset.h"
25 s->has_vmcoreinfo = offset == 0 && len == sizeof(s->vmcoreinfo) in fw_cfg_vmci_write()
26 && s->vmcoreinfo.guest_format != FW_CFG_VMCOREINFO_FORMAT_NONE; in fw_cfg_vmci_write()
33 s->has_vmcoreinfo = false; in vmcoreinfo_reset_hold()
34 memset(&s->vmcoreinfo, 0, sizeof(s->vmcoreinfo)); in vmcoreinfo_reset_hold()
35 s->vmcoreinfo.host_format = cpu_to_le16(FW_CFG_VMCOREINFO_FORMAT_ELF); in vmcoreinfo_reset_hold()
42 /* for gdb script dump-guest-memory.py */ in vmcoreinfo_realize()
54 if (!fw_cfg || !fw_cfg->dma_enabled) { in vmcoreinfo_realize()
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/qemu/include/hw/intc/
H A Dmips_gic.h33 #define MSK(n) ((1ULL << (n)) - 1)
49 /* Shared Global Counter */
57 /* Reset Mask - Disables Interrupt */
61 /* Set Mask (WO) - Enables Interrupt */
65 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
69 /* Pending Global Interrupts (RO) */
101 /* User-Mode Visible Section Register */
102 /* Read-only alias for GIC Shared CounterLo */
104 /* Read-only alias for GIC Shared CounterHi */
173 #define TYPE_MIPS_GIC "mips-gic"
/qemu/rust/hw/timer/hpet/src/
H A Ddevice.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
78 /// bit 4, 5, 15, and bits 32:64 are read-only.
88 /// Timer N Size (timer size is 64-bits or 32 bits, bit 5)
92 /// Timer N 32-bit Mode (bit 8)
120 /// Global registers
133 /// Global register in the range from `0` to `0xff`
134 Global(GlobalRegister), enumerator
150 const fn hpet_next_wrap(cur_tick: u64) -> u64 { in hpet_next_wrap()
154 const fn hpet_time_after(a: u64, b: u64) -> bool { in hpet_time_after()
155 ((b - a) as i64) < 0 in hpet_time_after()
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/qemu/hw/mips/
H A Dcps.c25 #include "hw/qdev-clock.h"
26 #include "hw/qdev-properties.h"
28 #include "system/reset.h"
32 assert(pin_number < s->num_irq); in get_cps_irq()
33 return s->gic.irq_state[pin_number].irq; in get_cps_irq()
41 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0); in mips_cps_init()
46 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); in mips_cps_init()
47 sysbus_init_mmio(sbd, &s->container); in mips_cps_init()
60 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
71 if (!clock_get(s->clock)) { in mips_cps_realize()
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/qemu/docs/system/arm/
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
22 - ``quanta-gbs-bmc`` Quanta GBS server BMC
23 - ``quanta-gsj`` Quanta GSJ server BMC
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/qemu/hw/core/
H A Dresettable.c10 * See the COPYING file in the top-level directory.
29 * True if we are currently in reset enter phase.
34 * Note: These flags are only used to guarantee (using asserts) that the reset
35 * API is used correctly. We can use global variables because we rely on the
36 * iothread mutex to ensure only one reset operation is in a progress at a
70 exit_phase_in_progress -= 1; in resettable_release_reset()
78 ResettableState *s = rc->get_state(obj); in resettable_is_in_reset()
80 return s->count > 0; in resettable_is_in_reset()
91 if (rc->child_foreach) { in resettable_child_foreach()
92 rc->child_foreach(obj, cb, opaque, type); in resettable_child_foreach()
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/qemu/tests/tcg/tricore/c/
H A Dcrt0-tc2x.S2 * crt0-tc2x.S -- Startup code for GNU/TriCore applications.
4 * Copyright (C) 1998-2014 HighTec EDV-Systeme GmbH.
28 * is built-in defined in tricore-c.c (from tricore-devices.c)
35 .global _start
82 * initialize access to system global registers
93 .global _SMALL_DATA_,_SMALL_DATA2_,_SMALL_DATA3_,_SMALL_DATA4_
106 * reset access to system global registers
156 .global __init_csa
171 sh %d2,%d2,-6 #; %d2 = number of CSAs
178 lea %a3,[%a3]64 #; %a3 = %a3->nextCSA
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/qemu/hw/i386/
H A Dtrace-events3 # x86-iommu.c
4 x86_iommu_iec_notify(bool global, uint32_t index, uint32_t mask) "Notify IEC invalidation: global=%…
12 vtd_inv_desc_iotlb_global(void) "iotlb invalidate global"
32 …date bus 0x%"PRIx8" devfn 0x%"PRIx8" high 0x%"PRIx64" low 0x%"PRIx64" gen %"PRIu32" -> gen %"PRIu32
33 vtd_iotlb_reset(const char *reason) "IOTLB reset (reason: %s)"
37 … start, uint64_t end) "walk (base=0x%"PRIx64", level=%"PRIu32") iova range 0x%"PRIx64" - 0x%"PRIx64
38 …uint64_t gpa, uint64_t mask, int perm) "domain 0x%"PRIx16" iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mas…
41 vtd_page_walk_skip_read(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRIx64…
42 vtd_page_walk_skip_reserve(uint64_t iova, uint64_t next) "Page walk skip iova 0x%"PRIx64" - 0x%"PRI…
56 …4_t iova, uint64_t gpa, uint64_t mask) "dev %02x:%02x.%02x iova 0x%"PRIx64" -> gpa 0x%"PRIx64" mas…
[all …]
/qemu/target/avr/
H A Dhelper.c4 * Copyright (c) 2016-2020 Michael Rolnik
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
23 #include "qemu/error-report.h"
25 #include "accel/tcg/cpu-ops.h"
27 #include "exec/page-protection.h"
29 #include "accel/tcg/cpu-ldst.h"
30 #include "exec/helper-proto.h"
41 if (env->skip) { in avr_cpu_exec_interrupt()
47 cs->exception_index = EXCP_RESET; in avr_cpu_exec_interrupt()
50 cs->interrupt_request &= ~CPU_INTERRUPT_RESET; in avr_cpu_exec_interrupt()
[all …]
/qemu/hw/ide/
H A Dahci-internal.h28 #include "ide-internal.h"
57 /* global controller registers */
60 AHCI_HOST_REG_CTL = 1, /* GHC: global host control */
74 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
75 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
82 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
84 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
145 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
186 /* ap->flags bits */
193 #define ATA_SRST (1 << 2) /* software reset */
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/qemu/docs/devel/
H A Dmulti-thread-tcg.rst2 Copyright (c) 2015-2020 Linaro Ltd.
5 later. See the COPYING file in the top-level directory.
10 Multi-threaded TCG
13 This document outlines the design for multi-threaded TCG (a.k.a MTTCG)
14 system-mode emulation. user-mode emulation has always mirrored the
17 linux-user emulation.
19 The original system-mode TCG implementation was single threaded and
20 dealt with multiple CPUs with simple round-robin scheduling. This
22 being emulated gained additional cores and per-core performance gains
29 user-space thread. This is enabled by default for all FE/BE
[all …]
/qemu/hw/usb/
H A Dhcd-dwc3.c4 * This model defines global register space of DWC3 controller. Global
7 * only supporting core reset and read of ID register.
36 #include "hw/qdev-properties.h"
37 #include "hw/usb/hcd-dwc3.h"
354 * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID, in reset_csr()
377 register_reset(&s->regs_info[i]); in reset_csr()
382 xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); in reset_csr()
387 USBDWC3 *s = USB_DWC3(reg->opaque); in usb_dwc3_gctl_postw()
389 if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { in usb_dwc3_gctl_postw()
396 USBDWC3 *s = USB_DWC3(reg->opaque); in usb_dwc3_guid_postw()
[all …]
/qemu/target/rx/
H A Dcpu.h24 #include "cpu-qom.h"
26 #include "exec/cpu-common.h"
27 #include "exec/cpu-defs.h"
28 #include "exec/cpu-interrupt.h"
29 #include "qemu/cpu-float.h"
88 uint32_t isp; /* global base register */
96 /* Fields up to this point are cleared by a CPU reset */
124 * @parent_phases: The parent class' reset phase handlers.
159 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); in rx_cpu_pack_psw()
160 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); in rx_cpu_pack_psw()
[all …]
/qemu/plugins/
H A Dplugin.h7 * See the COPYING file in the top-level directory.
9 * SPDX-License-Identifier: GPL-2.0-or-later
21 /* global state */
39 * @lock protects the struct as well as ctx->uninstalling.
80 bool reset);
123 * qemu_plugin_fillin_mode_info() - populate mode specific info
/qemu/target/sh4/
H A Dcpu.h23 #include "cpu-qom.h"
24 #include "exec/cpu-common.h"
25 #include "exec/cpu-defs.h"
26 #include "exec/cpu-interrupt.h"
27 #include "qemu/cpu-float.h"
151 uint32_t gbr; /* global base register */
153 uint32_t sgr; /* saved global register 15 */
191 /* LDST = LOCK_ADDR != -1. */
195 /* Fields up to this point are cleared by a CPU reset */
198 /* Fields from here on are preserved over CPU reset. */
[all …]
/qemu/include/hw/
H A Dqdev-core.h22 * -----------
31 * information to the caller and must be re-entrant.
57 * ---------------
62 * DeviceListener can save the QOpts passed to it for re-using it
73 DEV_NVECTORS_UNSPECIFIED = -1,
101 * struct DeviceClass - The base class for all devices.
107 * @sync_config: Callback function invoked when QMP command device-sync-config
136 * ensures a compile-time error if someone attempts to assign
137 * dc->props directly.
148 * @user_creatable: Can user instantiate with -device / device_add?
[all …]
/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h2 * STM32L4X5 RCC (Reset and clock control)
4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
24 #define TYPE_STM32L4X5_RCC "stm32l4x5-rcc"
76 /* - AHB1 */
83 /* - AHB2 */
96 /* - AHB3 */
[all …]
/qemu/hw/watchdog/
H A Dwdt_ib700.c52 /* This is the timer. We use a global here because the watchdog
70 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); in ib700_write_enable_reg()
80 timer_del(s->timer); in ib700_write_disable_reg()
91 timer_del(s->timer); in ib700_timer_expired()
116 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ib700_timer_expired, s); in wdt_ib700_realize()
118 portio_list_init(&s->port_list, OBJECT(s), wdt_portio_list, s, "ib700"); in wdt_ib700_realize()
119 portio_list_add(&s->port_list, isa_address_space_io(&s->parent_obj), 0); in wdt_ib700_realize()
126 ib700_debug("watchdog reset\n"); in wdt_ib700_reset()
128 timer_del(s->timer); in wdt_ib700_reset()
135 dc->realize = wdt_ib700_realize; in wdt_ib700_class_init()
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