3 // SPDX-License-Identifier: GPL-2.0-or-later
78 /// bit 4, 5, 15, and bits 32:64 are read-only.
88 /// Timer N Size (timer size is 64-bits or 32 bits, bit 5)
92 /// Timer N 32-bit Mode (bit 8)
120 /// Global registers
133     /// Global register in the range from `0` to `0xff`
134     Global(GlobalRegister),  enumerator
150 const fn hpet_next_wrap(cur_tick: u64) -> u64 {  in hpet_next_wrap()
154 const fn hpet_time_after(a: u64, b: u64) -> bool {  in hpet_time_after()
155     ((b - a) as i64) < 0  in hpet_time_after()
158 const fn ticks_to_ns(value: u64) -> u64 {  in ticks_to_ns()
162 const fn ns_to_ticks(value: u64) -> u64 {  in ns_to_ticks()
167 const fn hpet_fixup_reg(new: u64, old: u64, mask: u64) -> u64 {  in hpet_fixup_reg()
171 const fn activating_bit(old: u64, new: u64, shift: usize) -> bool {  in activating_bit()
176 const fn deactivating_bit(old: u64, new: u64, shift: usize) -> bool {  in deactivating_bit()
196     // Memory-mapped, software visible timer registers
209     /// timer pop will indicate wrap for one-shot 32-bit
217     fn new(index: u8, state: *const HPETState) -> HPETTimer {  in new()
242     fn get_state(&self) -> &HPETState {  in get_state()
248     fn is_int_active(&self) -> bool {  in is_int_active()
252     const fn is_fsb_route_enabled(&self) -> bool {  in is_fsb_route_enabled()
256     const fn is_periodic(&self) -> bool {  in is_periodic()
260     const fn is_int_enabled(&self) -> bool {  in is_int_enabled()
264     const fn is_32bit_mod(&self) -> bool {  in is_32bit_mod()
268     const fn is_valset_enabled(&self) -> bool {  in is_valset_enabled()
277     const fn is_int_level_triggered(&self) -> bool {  in is_int_level_triggered()
282     /// target (either entirely, or the low 32-bit only depending on
284     fn calculate_cmp64(&self, cur_tick: u64, target: u64) -> u64 {  in calculate_cmp64()
296     const fn get_individual_route(&self) -> usize {  in get_individual_route()
300     fn get_int_route(&self) -> usize {  in get_int_route()
303             // timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,  in get_int_route()
304             // timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.  in get_int_route()
316             // (If the LegacyReplacement Route bit is set) Timer 2-n will be  in get_int_route()
364         if self.is_periodic() && ns - self.last < 1000 {  in arm_timer()
378             // HPET spec says in one-shot 32-bit mode, generate an interrupt when  in set_timer()
395             // For level-triggered interrupt, this leaves interrupt status  in del_timer()
403         // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4)  in set_tn_cfg_reg()
408         // Switch level-type interrupt to edge-type.  in set_tn_cfg_reg()
436         // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4)  in set_tn_cmp_reg()
438             // High 32-bits are zero, leave them untouched.  in set_tn_cmp_reg()
440                 // TODO: Add trace point - trace_hpet_ram_write_invalid_tn_cmp()  in set_tn_cmp_reg()
466     fn reset(&mut self) {  in reset()  method
468         self.cmp = u64::MAX; // Comparator Match Registers reset to all 1's.  in reset()
502     const fn read(&self, reg: TimerRegister) -> u64 {  in read()
528     // HPET block Registers: Memory-mapped, software visible registers
571     const fn has_msi_flag(&self) -> bool {  in has_msi_flag()
575     fn is_legacy_mode(&self) -> bool {  in is_legacy_mode()
579     fn is_hpet_enabled(&self) -> bool {  in is_hpet_enabled()
583     fn is_timer_int_active(&self, index: usize) -> bool {  in is_timer_int_active()
587     fn get_ticks(&self) -> u64 {  in get_ticks()
591     fn get_ns(&self, tick: u64) -> u64 {  in get_ns()
592         ticks_to_ns(tick) - self.hpet_offset.get()  in get_ns()
639                 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns());  in set_cfg_reg()
664             // TODO: Add irq binding: qemu_irq_lower(s->irqs[0])  in set_cfg_reg()
686             // TODO: Add trace point -  in set_counter_reg()
727     fn realize(&self) -> qemu_api::Result<()> {  in realize()
734             Err("hpet.hpet-intcap property not initialized")?;  in realize()
739         // 64-bit General Capabilities and ID Register; LegacyReplacementRoute.  in realize()
745             ((self.num_timers - 1) as u64) << HPET_CAP_NUM_TIM_SHIFT | // indicate the last timer  in realize()
756             timer.borrow_mut().reset();  in reset_hold()
770         // to document that the RTC lowers its output on reset as well  in reset_hold()
774     fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAddrDecode<'_> {  in decode()
776         let len = std::cmp::min(size * 8, 64 - shift);  in decode()
780             GlobalRegister::try_from(addr).map(HPETRegister::Global)  in decode()
782             let timer_id: usize = ((addr - 0x100) / 0x20) as usize;  in decode()
784                 // TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)  in decode()
788                 // TODO: Add trace point -  trace_hpet_timer_id_out_of_range(timer_id)  in decode()
799     fn read(&self, addr: hwaddr, size: u32) -> u64 {  in read()
800         // TODO: Add trace point - trace_hpet_ram_read(addr)  in read()
807             Global(CAP) => self.capability.get(), /* including HPET_PERIOD 0x004 */  in read()
808             Global(CFG) => self.config.get(),  in read()
809             Global(INT_STATUS) => self.int_status.get(),  in read()
810             Global(COUNTER) => {  in read()
820                 // TODO: Add trace point- trace_hpet_ram_read_invalid()  in read()
829         // TODO: Add trace point - trace_hpet_ram_write(addr, value)  in write()
834             Global(CAP) => {} // General Capabilities and ID Register: Read Only  in write()
835             Global(CFG) => self.set_cfg_reg(shift, len, value),  in write()
836             Global(INT_STATUS) => self.set_int_status_reg(shift, len, value),  in write()
837             Global(COUNTER) => self.set_counter_reg(shift, len, value),  in write()
839                 // TODO: Add trace point - trace_hpet_ram_write_invalid()  in write()
844     fn pre_save(&self) -> i32 {  in pre_save()
858     fn post_load(&self, _version_id: u8) -> i32 {  in post_load()
863             t.last = CLOCK_VIRTUAL.get_ns() - NANOSECONDS_PER_SECOND;  in post_load()
869                 .set(ticks_to_ns(self.counter.get()) - CLOCK_VIRTUAL.get_ns());  in post_load()
875     fn is_rtc_irq_level_needed(&self) -> bool {  in is_rtc_irq_level_needed()
879     fn is_offset_needed(&self) -> bool {  in is_offset_needed()
883     fn validate_num_timers(&self, _version_id: u8) -> bool {  in validate_num_timers()
904 // TODO: Make these properties user-configurable!
925         c"hpet-intcap",
933         c"hpet-offset-saved",
942 unsafe extern "C" fn hpet_rtc_irq_level_needed(opaque: *mut c_void) -> bool {  in hpet_rtc_irq_level_needed()
949 unsafe extern "C" fn hpet_offset_needed(opaque: *mut c_void) -> bool {  in hpet_offset_needed()
956 unsafe extern "C" fn hpet_pre_save(opaque: *mut c_void) -> c_int {  in hpet_pre_save()
964 unsafe extern "C" fn hpet_post_load(opaque: *mut c_void, version_id: c_int) -> c_int {  in hpet_post_load()
1035     fn properties() -> &'static [Property] {  in properties()
1039     fn vmsd() -> Option<&'static VMStateDescription> {  in vmsd()
1043     const REALIZE: Option<fn(&Self) -> qemu_api::Result<()>> = Some(Self::realize);