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/qemu/target/riscv/
H A Ddebug.c2 * QEMU RISC-V Native Debug Support
9 * This provides the native debug support via the Trigger Module, as defined
10 * in the RISC-V Debug Specification:
11 * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
31 #include "exec/helper-proto.h"
33 #include "system/cpu-timers.h"
37 * The following M-mode trigger CSRs are implemented:
39 * - tselect
40 * - tdata1
41 * - tdata2
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/qemu/hw/intc/
H A Dxive.c4 * Copyright (c) 2017-2018, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
17 #include "hw/qdev-properties.h"
35 return tctx->os_output; in xive_tctx_output()
38 return tctx->hv_output; in xive_tctx_output()
39 default: in xive_tctx_output()
46 uint8_t *regs = &tctx->regs[ring]; in xive_tctx_accept()
62 alt_regs = &tctx->regs[alt_ring]; in xive_tctx_accept()
79 trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring, in xive_tctx_accept()
91 uint8_t *alt_regs = &tctx->regs[alt_ring]; in xive_tctx_notify()
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H A Daspeed_vic.c9 * the COPYING file in the top-level directory.
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
75 /* level-triggered */ in aspeed_vic_set_irq()
76 if (s->event & irq_mask) { in aspeed_vic_set_irq()
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H A Drx_icu.c11 * SPDX-License-Identifier: GPL-2.0-or-later
28 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
66 if ((icu->fir & R_FIR_FIEN_MASK) && in set_irq()
67 (icu->fir & R_FIR_FVCT_MASK) == n_IRQ) { in set_irq()
68 qemu_set_irq(icu->_fir, req); in set_irq()
70 qemu_set_irq(icu->_irq, req); in set_irq()
76 return (icu->ipr[icu->map[n]] << 8) | n; in rxicu_level()
83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); in rxicu_request()
84 if (n_IRQ > 0 && enable != 0 && qatomic_read(&icu->req_irq) < 0) { in rxicu_request()
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H A Dppc-uic.c26 #include "hw/intc/ppc-uic.h"
28 #include "hw/qdev-properties.h"
57 /* Trigger interrupt if any is pending */ in ppcuic_trigger_irq()
58 ir = uic->uicsr & uic->uicer & (~uic->uiccr); in ppcuic_trigger_irq()
59 cr = uic->uicsr & uic->uicer & uic->uiccr; in ppcuic_trigger_irq()
63 __func__, uic->uicsr, uic->uicer, uic->uiccr, in ppcuic_trigger_irq()
64 uic->uicsr & uic->uicer, ir, cr); in ppcuic_trigger_irq()
67 qemu_irq_raise(uic->output_int); in ppcuic_trigger_irq()
70 qemu_irq_lower(uic->output_int); in ppcuic_trigger_irq()
72 /* Trigger critical interrupt if any is pending and update vector */ in ppcuic_trigger_irq()
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H A Dxive2.c4 * Copyright (c) 2019-2024, IBM Corporation..
6 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/qdev-properties.h"
26 return xrc->get_config(xrtr); in xive2_router_get_config()
33 return xrc->get_block_id(xrtr); in xive2_router_get_block_id()
40 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | in xive2_nvp_reporting_addr()
41 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); in xive2_nvp_reporting_addr()
56 * The per-priority backlog counters are 24-bit and the structure in xive2_nvgc_get_backlog()
57 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from in xive2_nvgc_get_backlog()
58 * w2, which fits 8 priorities * 24-bits per priority. in xive2_nvgc_get_backlog()
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/qemu/include/hw/
H A Dptimer.h19 * When it reaches zero it will trigger a callback function, and
21 * and keep counting down, or to stop (as a one-shot timer).
23 * A transaction-based API is used for modifying ptimer state: all calls
29 * list of state-modifying functions and detailed semantics of the callback.)
48 * The rough edges of the default policy:
49 * - Starting to run with a period = 0 emits error message and stops the
50 * timer without a trigger.
52 * - Setting period to 0 of the running timer emits error message and
53 * stops the timer without a trigger.
55 * - Starting to run with counter = 0 or setting it to "0" while timer
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/qemu/hw/ppc/
H A Dpnv_chiptod.c4 * Copyright (c) 2022-2023, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 * purpose is to keep time-of-day across chips and cores.
32 #include "hw/qdev-properties.h"
53 /* -- TOD primary/secondary master/slave control register -- */
56 /* -- TOD primary/secondary master/slave status register -- */
78 /* -- TOD Error interrupt register -- */
86 * - The reset state is 0 error.
87 * - A hardware error detected will transition to state 0 from any state.
88 * - LOAD_TOD_MOD and TTYPE5 will transition to state 7 from any state.
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/qemu/hw/gpio/
H A Dnpcm7xx_gpio.c20 #include "hw/qdev-properties.h"
28 /* 32-bit register indices. */
70 uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN]; in npcm7xx_gpio_update_events()
72 /* Trigger on high level */ in npcm7xx_gpio_update_events()
73 s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP]; in npcm7xx_gpio_update_events()
74 /* Trigger on both edges */ in npcm7xx_gpio_update_events()
75 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP] in npcm7xx_gpio_update_events()
76 & s->regs[NPCM7XX_GPIO_EVBE]); in npcm7xx_gpio_update_events()
77 /* Trigger on rising edge */ in npcm7xx_gpio_update_events()
78 s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new in npcm7xx_gpio_update_events()
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/qemu/hw/timer/
H A Dstellaris-gptm.c15 #include "hw/qdev-clock.h"
16 #include "hw/timer/stellaris-gptm.h"
21 level = (s->state & s->mask) != 0; in gptm_update_irq()
22 qemu_set_irq(s->irq, level); in gptm_update_irq()
27 timer_del(s->timer[n]); in gptm_stop()
36 tick = s->tick[n]; in gptm_reload()
39 if (s->config == 0) { in gptm_reload()
40 /* 32-bit CountDown. */ in gptm_reload()
42 count = s->load[0] | (s->load[1] << 16); in gptm_reload()
43 tick += clock_ticks_to_ns(s->clk, count); in gptm_reload()
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/qemu/tests/qtest/
H A Dpnv-xive2-test.c3 * - Test irq to hardware thread
4 * - Test 'Pull Thread Context to Odd Thread Reporting Line'
5 * - Test irq to hardware group
6 * - Test irq to hardware group going through backlog
7 * - Test irq to pool thread
11 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "pnv-xive2-common.h"
50 default: in set_table()
55 log_size = ctzl(XIVE_VST_SIZE) - 12; in set_table()
148 size_t mem_used = XIVE_MEM_END - XIVE_MEM_START; in reset_state()
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/qemu/docs/devel/testing/
H A Dfuzzing.rst5 This document describes the virtual-device fuzzing infrastructure in QEMU and
9 ------
16 is an *in-process* fuzzer. For the developer, this means that it is their
17 responsibility to ensure that state is reset between fuzzing-runs.
20 --------------------
24 Here, enable-asan and enable-ubsan are optional but they allow us to reliably
25 detect bugs such as out-of-bounds accesses, uses-after-free, double-frees
28 CC=clang-8 CXX=clang++-8 /path/to/configure \
29 --enable-fuzzing --enable-asan --enable-ubsan
33 make qemu-fuzz-i386
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H A Dblkdebug.rst5 Copyright (C) 2014-2015 Red Hat Inc
8 the COPYING file in the top-level directory.
10 The ``blkdebug`` block driver is a rule-based error injection engine. It can be
17 ----------
23 Error injection allows test cases to trigger I/O errors at specific points.
27 -----
35 follows the same .ini-like format used by QEMU's ``-readconfig`` option, and
41 [inject-error]
47 ``/usr/include/asm-generic/errno-base.h`` for errno values.
51 $ qemu-system-x86_64
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/qemu/qapi/
H A Dmigration.json1 # -*- Mode: Python -*-
28 # @normal-bytes: number of normal bytes sent (since 1.2)
30 # @dirty-pages-rate: number of pages dirtied by second by the guest
35 # @dirty-sync-count: number of times that dirty ram was synchronized
38 # @postcopy-requests: The number of page requests received from the
41 # @page-size: The number of bytes per page for the various page-based
44 # @multifd-bytes: The number of bytes sent through multifd (since 3.0)
46 # @pages-per-second: the number of memory pages transferred per second
49 # @precopy-bytes: The number of bytes sent in the pre-copy phase
52 # @downtime-bytes: The number of bytes sent while the guest is paused
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/qemu/docs/system/i386/
H A Dmicrovm.rst8 designed for short-lived guests. microvm also establishes a baseline
14 -----------------
18 - ISA bus
19 - i8259 PIC (optional)
20 - i8254 PIT (optional)
21 - MC146818 RTC (optional)
22 - One ISA serial port (optional)
23 - LAPIC
24 - IOAPIC (with kernel-irqchip=split by default)
25 - kvmclock (if using KVM)
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/qemu/docs/system/s390x/
H A Dprotvirt.rst12 -------------
26 -----------------------------------
32 -object s390-pv-guest,id=pv0 \
33 -machine confidential-guest-support=pv0
38 * Enable the IOMMU by default for all I/O devices
48 ------------
52 s390-ccw BIOS. I.e., the bootmap is interpreted, multiple components
57 (stage3a) that uses the new diag308 subcodes 8 and 10 to trigger the
61 the file passed via -kernel has the same memory layout as would result
65 options -initrd and -cmdline are ineffective. The preparation of a PVM
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/qemu/tests/qemu-iotests/
H A D2894 # qcow2 v3-exclusive error path testing
26 status=1 # failure is the default!
32 rm -f "$TEST_IMG.data_file"
43 # This is a v3-exclusive test;
54 [inject-error]
62 _make_test_img -o "data_file=$TEST_IMG.data_file" 64k
64 # Put blkdebug above the data-file, and a raw node on top of that so
66 # will then trigger the alloc abort code, which we want to test here.
67 $QEMU_IO -c "write 0 64k" \
71 'data-file': {
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H A D03328 status=1 # failure is the default!
56 IO_EXTRA_ARGS="--image-opts"
58 IO_OPEN_ARG="-o driver=$IMGFMT,file.align=$align blkdebug::$img"
70 for write_zero_cmd in "write -z" "aio_write -z"; do
74 do_test $align "write -P 0xa 0x200 0x400" "$TEST_IMG" | _filter_qemu_io
75 do_test $align "write -P 0xa 0x20000 0x600" "$TEST_IMG" | _filter_qemu_io
80 do_test $align "read -P 0xa 0x200 0x200" "$TEST_IMG" | _filter_qemu_io
81 do_test $align "read -P 0x0 0x400 0x20000" "$TEST_IMG" | _filter_qemu_io
82 do_test $align "read -P 0xa 0x20400 0x200" "$TEST_IMG" | _filter_qemu_io
86 do_test $align "write -P 0xb 0x10000 0x10000" "$TEST_IMG" | _filter_qemu_io
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H A D02628 status=1 # failure is the default!
34 rm -f "$TEST_IMG.data_file"
50 # being the default refcount entry width.
86 for vmstate in "" "-b"; do
89 [inject-error]
103 $QEMU_IO -c "write $vmstate 0 512" "$TEST_IMG" > /dev/null 2>&1
106 $QEMU_IO -c "write $vmstate 0 128k " "$BLKDBG_TEST_IMG" | _filter_qemu_io
109 # Reads are another path to trigger l2_load, so do a read, too
111 $QEMU_IO -c "write $vmstate 0 128k " "$BLKDBG_TEST_IMG" | _filter_qemu_io
112 $QEMU_IO -c "read $vmstate 0 128k " "$BLKDBG_TEST_IMG" | _filter_qemu_io
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H A D12128 status=1 # failure is the default!
51 echo '--- Test 1 ---'
57 _make_test_img -o 'preallocation=metadata,cluster_size=1k' 64512K
70 # (Note that for some reason, 'write 63M 1K' does not trigger the problem)
71 $QEMU_IO -c 'write 62M 1025K' -c 'write 64M 1M' "$TEST_IMG" | _filter_qemu_io
77 echo '--- Test 2 ---'
80 _make_test_img -o 'preallocation=metadata,cluster_size=1k' 64513K
87 # and is thus not self-describing (in contrast to test 1, where new_block was
88 # self-describing). The refcount table growth algorithm then used to place the
94 # to be self-describing).
[all …]
/qemu/include/standard-headers/linux/
H A Dinput.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 1999-2002 Vojtech Pavlik
15 #include "standard-headers/linux/types.h"
17 #include "standard-headers/linux/input-event-codes.h"
53 * IOCTLs (0x00 - 0x7f)
64 * struct input_absinfo - used by EVIOCGABS/EVIOCSABS ioctls
78 * The default resolution for main axes (ABS_X, ABS_Y, ABS_Z,
100 * struct input_keymap_entry - used by EVIOCGKEYCODE/EVIOCSKEYCODE ioctls
101 * @scancode: scancode represented in machine-endian form.
145 * EVIOCGMTSLOTS(len) - get MT slot values
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/qemu/hw/pci-host/
H A Dpnv_phb4.c4 * Copyright (c) 2018-2020, IBM Corporation.
7 * COPYING file in the top-level directory.
14 #include "hw/pci-host/pnv_phb4_regs.h"
15 #include "hw/pci-host/pnv_phb4.h"
21 #include "hw/qdev-properties.h"
27 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__)
31 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
35 PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); in pnv_phb4_find_cfg_dev()
36 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; in pnv_phb4_find_cfg_dev()
49 return pci_find_device(pci->bus, bus, devfn); in pnv_phb4_find_cfg_dev()
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/qemu/docs/about/
H A Demulation.rst9 .. list-table:: Supported Guest Architectures for Emulation
11 :header-rows: 1
13 * - Architecture (qemu name)
14 - System
15 - User
16 - Notes
17 * - Alpha
18 - Yes
19 - Yes
20 - Legacy 64 bit RISC ISA developed by DEC
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/qemu/tests/qemu-iotests/tests/
H A Dfile-io-error4 # Produce an I/O error in file-posix, and hope that it is not catastrophic.
26 status=1 # failure is the default!
31 rm -f "$TEST_DIR/fuse-export"
40 # Format-agnostic (we do not use any), but we do test the file protocol
42 _require_drivers blkdebug null-co
45 # We need `$QEMU_IO -f file` to work; IMGOPTSSYNTAX uses --image-opts,
46 # breaking -f.
50 # This is a regression test of a bug in which flie-posix would access zone
53 # To reproduce the problem, we need to trigger an I/O error inside of
54 # file-posix, which can be done (rootless) by providing a FUSE export that
[all …]
/qemu/docs/tools/
H A Dqemu-nbd.rst1 .. _qemu-nbd:
8 --------
10 **qemu-nbd** [*OPTION*]... *filename*
12 **qemu-nbd** -L [*OPTION*]...
14 **qemu-nbd** -d *dev*
17 -----------
23 - Bind a /dev/nbdX block device to a QEMU server (on Linux).
24 - As a client to query exports of a remote NBD server.
27 -------
29 .. program:: qemu-nbd
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